Flash analog-to-digital converter using folded differential...

Details Flash analog-to-digital converter using folded differential... Flash analog-to-digital converter using folded differential...

2002-01-11

2003-04-01

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S118000, C341S158000, C341S155000, C341S163000, C365S203000, C365S149000

Reexamination Certificate

active

06542107

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to analog-to-digital converters, and specifically to analog-to-digital converters having folded differential logic encoding architectures.
BACKGROUND OF THE INVENTION
As speeds of operation of electronic equipment increase, analog-to-digital converters (ADCs) need to operate at increasing rates in order not become a bottleneck in the operation of the equipment. A known architecture in the electronic art, which inherently comprises a fast system for analog-to-digital conversion, is “flash” architecture, wherein a number of comparators operate simultaneously and in parallel. The readout of a flash ADC is substantially a “one-step” process.
FIG. 1
is a schematic block diagram of an m-bit flash analog-to-digital converter (ADC)
10
, as is known in the art. Flash ADC
10
comprises a series resistor ladder
12
, having 2
m
equal valued resistors coupled to a first reference voltage Vr
1
and a second reference voltage Vr
2
, which generate 2
m
sequential potentials. The potentials are respectively applied to a first input of 2
m
comparators
14
, which have a voltage Vin to be digitized applied to a second input of the comparators. The output of the comparators is in the form of thermometer code, which is converted to binary code by a decoder
16
. Decoder
16
typically uses conversion from thermometer code to Gray code as an intermediate step, in order to reduce the effects of sparkles and meta-stability in the thermometer code. ADC
10
is typically implemented as a very large scale integrated circuit (VLSI).
FIG. 2
is a schematic electronic diagram of a 3-bit ADC
20
using a folded differential logic (FDL) architecture, and giving a Gray code output, as is known in the art. A series ladder
21
, which is driven by reference potentials Vr
1
and Vr
2
, and an analog voltage input line
23
provide input levels to comparators
22
A,
22
B, . . . ,
22
G. Thermometer code outputs, and their inverses, are generated as differential outputs by the comparators. The differential outputs of comparators
22
A,
22
B, . . . ,
22
G are herein termed (T
1
,{overscore (T
1
)}), (T
2
,{overscore (T
2
)}), . . . , (T
7
,{overscore (T
7
)}) respectively. Differential outputs (T
1
,{overscore (T
1
)}), (T
2
,{overscore (T
2
)}), . . . , (T
7
,{overscore (T
7
)}) are input to respective differential pairs of transistors
24
A,
24
B, . . . ,
24
G. Each differential pair of transistors is driven by a current source delivering a current I
0
. As shown in the diagram, the outputs of groups of the differential pairs are added, and the summed outputs generate respective potentials across resistors
25
A,
25
B, . . . ,
25
F. The outputs of the differential pairs are connected to comparators
26
,
28
, and
30
, so as to generate Gray code outputs D
0
, D
1
, and D
2
respectively.
Thus, comparator
26
, generating the least significant bit (LSB), receives its potential inputs from current source
32
(delivering a current I
0
) and differential pairs
24
A,
24
C,
24
E, and
24
G feeding through resistors
25
E and
25
F. Since four differential pairs are summed, comparator
26
has a folding factor of
4
. The inputs to comparator
26
are generated on lines
27
and
29
, which have a voltage corresponding to T
1
+{overscore (T
3
)}+T
5
+{overscore (T
7
)}+
1
and a voltage corresponding to {overscore (T
1
)}+T
3
+{overscore (T
5
)}+T
7
respectively. Thus, comparator
26
forms its output for a value of the LSB by effectively comparing T
1
+{overscore (T
3
)}+T
5
+{overscore (T
7
)}+
1
with {overscore (T
1
)}+T
3
+{overscore (T
5
)}+T
7
.
Comparator
28
receives its potential inputs from a current source
34
and differential pairs
24
B and
24
F feeding through resistors
25
C and
25
D. Since two differential pairs are summed, comparator
28
has a folding factor of
2
. The inputs to comparator
28
correspond to T
2
+{overscore (T
6
)}+
1
and {overscore (T
2
)}+T
6
, and the comparator forms its output for a value of a first bit by effectively comparing T
2
+{overscore (T
6
)}+
1
with {overscore (T
2
)}+T
6
. Similarly, comparator
30
has inputs corresponding to T
4
and {overscore (T
4
)}, forming an output for a value of a most significant bit (MSB) by effectively comparing T
4
with {overscore (T
4
)}.
Analog-to-digital converters exemplified by ADC
20
use FDL architecture implemented with bipolar transistors. However, bipolar transistor technology suffers from a number of known disadvantages compared with complementary metal oxide semiconductor (CMOS) technology. For example, bipolar transistors dissipate significantly higher powers and require relatively larger areas of silicon substrate compared with CMOS transistors.
U.S. Pat. No. 6,014,098, to Bult et al., whose disclosure is incorporated herein by reference, describes an ADC implemented in a CMOS technology. Outputs of comparators of the ADC are fed through cascaded stages of averaging amplifiers. The stages comprise folding, so that the cascading effectively implements multiple folding.
SUMMARY OF THE INVENTION
In preferred embodiments of the present invention, a folded differential logic (FDL) encoder section of an analog-to-digital converter (ADC) operates by redistributing charges stored within two sub-sections of the encoder. The charges are stored on capacitors, preferably by means of transistors acting as capacitors. The redistribution is implemented by switching logic, preferably implemented by switching transistors. Both types of transistors are most preferably implemented using complementary metal oxide semiconductor (CMOS) technology, although other technologies may also be used to implement the transistors. Operating an FDL encoder by redistributing charges substantially reduces power dissipation, compared to encoders which operate by comparing currents, since there is substantially no current flowing from supply to ground. In addition, rates of operation of charge redistribution encoders are significantly faster, and less area of silicon substrate is required, than in encoders comparing currents. This ADC design is therefore particularly well suited for CMOS implementation.
Within each sub-section of the FDL encoder, a primary capacitor is charged to an initial voltage. Each sub-section receives thermometer code which is produced in a thermometer code generator responsive to an analog input voltage. Within each sub-section the code activates a number of transistor switches, according to a value of the code, which are coupled to secondary capacitors. The charge is thereby redistributed between the primary capacitor and the number of the secondary capacitors that are coupled by the activated switches. The charge redistribution causes a voltage drop from the initial voltage, the drop being a function of the number of secondary capacitors receiving the charge, and thus of the thermometer code. The voltage drops in the two sub-sections are compared to generate an output bit corresponding to the input analog voltage.
Preferably, the ADC comprises a plurality of FDL encoder sections, each encoder section generating a specific bit corresponding to the analog input voltage.
There is therefore provided, according to a preferred embodiment of the present invention, an analog-to-digital converter, including:
a code generator, coupled to receive an input analog voltage and to one or more reference voltages, and adapted to generate a digital code responsive thereto; and
one or more folded differential logic encoders (FDLEs), each of the FDLEs including:
a plurality of capacitors; and
switching logic, coupled to receive the digital code and distribute a charge between the plurality of capacitors responsive to the received digital code, and to output a digital bit indicative of the input analog voltage responsive to a magnitude of a potential generated by the distributed charge on at least one of the plurality of capacitors.
Preferably, the code generator in

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