Flash analog-to-digital converter employing least significant bi

Details Flash analog-to-digital converter employing least significant bi Flash analog-to-digital converter employing least significant bi

1991-12-30

1993-03-16

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, H03M 136

Patent

active

051948672

ABSTRACT:
A flash analog-digital (A/D) coverter for producing an n-bit binary number whose value is related to an analog input voltage value includes a resistor ladder network having 2.sup.n-1 +1 nodes. Each node is coupled to a comparator stage to provide an intermediate reference voltage to the stage. Each stage has a first output at which is provided a first output voltage whose value depends on whether the input voltage exceeds the intermediate reference voltage, and a second output voltage whose value depends on whether the input voltage exceeds the intermediate reference voltage by a least significant bit voltage. A combinational logic network is coupled to the first outputs of the stages for decoding the n-1 most significant bits of the n-bit number based on the highest intermediate reference voltage which does not exceed the input voltage. The network is further coupled to the second outputs of the stages to enable the second output of the stage corresponding to the highest intermediate voltage that does not exceed the input voltage through to be the least significant bit of the n-bit number.

REFERENCES:
patent: 3877025 (1975-04-01), Maio
patent: 4600916 (1986-07-01), Masuda et al.
patent: 4928103 (1990-05-01), Lane
patent: 4965579 (1990-10-01), Liu et al.

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