Flash ADC receiver with reduced errors

Details Flash ADC receiver with reduced errors Flash ADC receiver with reduced errors

2005-12-27

2005-12-27

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S094000, C341S158000, C341S159000, C714S704000, C714S795000, C714S798000, C714S799000

Reexamination Certificate

active

06980140

ABSTRACT:
Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.

REFERENCES:
patent: 4823360 (1989-04-01), Tremblay et al.
patent: 5606540 (1997-02-01), Hayashi
patent: 5663945 (1997-09-01), Hayashi et al.
patent: 5809071 (1998-09-01), Kobayashi et al.
patent: 5896391 (1999-04-01), Solheim et al.
patent: 5944844 (1999-08-01), Piirainen et al.
patent: 6097769 (2000-08-01), Sayiner et al.
patent: 6307899 (2001-10-01), Starr et al.
patent: 6603416 (2003-08-01), Masenas et al.
patent: 6618436 (2003-09-01), Greiss et al.
patent: 6735259 (2004-05-01), Roberts et al.
patent: 6735724 (2004-05-01), McClellan
patent: 6877117 (2005-04-01), Childers et al.
patent: 6894985 (2005-05-01), Billhartz
patent: 2004/0030965 (2004-02-01), Hadjihassan et al.
patent: 2004/0091273 (2004-05-01), Brissette et al.

Affiliated with

Also associated with

Rating

Flash ADC receiver with reduced errors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flash ADC receiver with reduced errors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash ADC receiver with reduced errors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3517238