Flash A/D converter having reduced input loading

Details Flash A/D converter having reduced input loading Flash A/D converter having reduced input loading

1982-05-24

1985-03-26

Sloyan, T. J.

Communications: electrical

Audible indication

Percussion-type sound producer

307451, 307585, H03K 1302, H03K 13175

Patent

active

045076499

ABSTRACT:
A flash analog-to-digital converter includes 2.sup.N comparator circuits for an N bit resolution. Each comparator comprises a summing capacitor which is alternately connected to a reference ladder and to the input signal. The majority of the capacitors are substantially charged and discharged between input potential and reference potential each cycle. The charging/discharging tends to load both the reference ladder and the input signal source. The loading is reduced by including a D.C. biased FET between the input signal source and each summing capacitor. The FET's are biased to condition them to operate as source-followers with the summing capacitors as the load element for at least a portion of the input signal range. Respective ones of the summing capacitors are thereby precluded from charging/discharging over the full input signal excursion which in turn reduces loading on associated circuitry.

REFERENCES:
patent: 3676702 (1972-07-01), McGrogan, Jr.
"CMOS/SOS Flash ADC Speeds on Low Power for Low Cost", M. Glincman, Electronic Design, Nov. 22, 1980, pp. 227-231.

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