Coded data generation or conversion – Converter calibration or testing
Patent
1987-05-04
1988-12-27
Sloyan, T. J.
Coded data generation or conversion
Converter calibration or testing
307451, 307585, 341155, H03M 136
Patent
active
047943742
ABSTRACT:
An A/D converter comprises a resistor ladder connected between first and second reference potentials so that each connection tap provides a different divided reference potential. A plurality of first switches are each connected at their one end to one connection tap of the resistor ladder and at their other end to a corresponding number of common connection nodes. Also, a plurality of second switches are each connected at their one end commonly to an input for an analog voltage signal and at their other end to the corresponding common connection nodes. Each of the nodes is connected through one coupling capacitor to one amplifier having adapted to generate an output signal representative of whether the voltage of the input signal is higher or lower than a voltage appearing at the above mentioned one connection tap of the resistor ladder. Each of the amplifier has a third switch connected between the input and the output of the amplifier, and an encoder is connected to the output of each amplifier so as to generate an digital signal corresponding to the input analog signal. Each of the common connection nodes are connected through an associated fourth switch to a bias voltage source. In a pre-calibration period proceeding to a calibration period, the third and fourth switches are closed so that the respective common connection nodes are forcedly and rapidly charged or discharged through the bias voltage source.
REFERENCES:
patent: 4507649 (1985-03-01), Dingwall et al.
Fujita et al., A Bulk CMOS 20MS/s 7 b Flash ADC, 1984, IEEE International Solid-State Circuits Conference, pp. 56 and 57.
NEC Corporation
Sloyan T. J.
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