Flag-based high-speed I/O data transfer

Details Flag-based high-speed I/O data transfer Flag-based high-speed I/O data transfer

1994-10-11

1995-09-12

Powell, Mark R.

395162, G06F 1200

Patent

active

054505437

ABSTRACT:
A memory address pointer that selects a memory location that is mapped to a video graphics circuit port is incremented only when all bytes in a memory location have been read from or written to by the host CPU. This does not depend on the order in which the host CPU reads or writes data bytes. Therefore a video controller that uses the present invention will work with 8 bit, 16 bit as well as high performance 32 bit input/output instructions.

REFERENCES:
patent: 4347567 (1982-08-01), DeTar, Jr. et al.
patent: 4965723 (1990-10-01), Kirk et al.
patent: 5068785 (1991-11-01), Sugiyama
patent: 5369738 (1994-11-01), Bremner, III

Affiliated with

Also associated with

Rating

Flag-based high-speed I/O data transfer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Flag-based high-speed I/O data transfer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flag-based high-speed I/O data transfer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-412995