Fixed transconductance bias apparatus

Details Fixed transconductance bias apparatus Fixed transconductance bias apparatus

2001-02-20

2002-06-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S538000, C323S315000

Reexamination Certificate

active

06400185

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to fixed transconductance bias circuits.
BACKGROUND OF THE INVENTION
Many techniques can be used for a fixed transconductance bias circuit, but for the simplest implementations, it is common to slave the transconductance of the desired MOSFET to a precise off chip resistor. One of the prior art techniques that has been used is shown in FIG.
1
. The following model (Eq. 1) is assumed for a MOS transistor operating in strong inversion and saturation.
I
DS
=
μ
n
⁢
C
ox
′
2
⁢
α
⁢
(
W
L
)
⁢
(
V
GS
-
V
T
)
2
Eq
.
 
⁢
1
where all the symbols have their usual meanings which are well known in the art. Velocity saturation effects and finite drain conductance are also neglected. The current mirror formed by transistors M
3
and M
4
forces identical currents through transistors M
1
and M
2
.
I
M1
=
μ
n
⁢
C
ox
′
2
⁢
α
⁢
(
W
L
)
⁢
(
V
GS1
-
V
T
)
2
Eq
.
 
⁢
2
I
M2
=
μ
n
⁢
C
ox
′
2
⁢
α
⁢
(
4
⁢
W
L
)
⁢
(
V
GS2
-
V
T
)
2
Eq
.
 
⁢
3
 
I
M1
=I
M2
=I
  Eq. 4
 
V
GS1
−V
GS2
=IR
  Eq. 5
From Eq. 2, Eq. 3 and Eq. 4,
V
GS1
−V
T
=2(
V
GS2
−V
T
)  Eq. 6
From Eq. 5 and Eq. 6,
V
GS1
−V
T
=2
IR
  Eq. 7
and the transconductance of transistor M
1
is given by Eq.8,
g
m
&RightBracketingBar;
⁢
 
⁢
M1
=
(
2
⁢
I
V
GS1
-
V
T
)
=
1
R
Eq
.
 
⁢
8
The circuit thus stabilizes to a state where the current is such that the transconductance (g
m
) of M
1
is maintained at 1/R, if irrespective of V
T
,
&mgr;
, or temperature. This current can be used to bias other MOSFETs.
The prior art circuit of
FIG. 1
has the following problems. In n-well technologies, the body terminal of n-channel devices is constrained to be grounded. There will be an error in the set transconductance because transistors M
1
and M
2
do not have the same threshold voltages any more. Another problem, which arises when this circuit is used with short channel transistors, is that the MOSFET is no longer a square law device, and this causes significant error.
There is sensitivity to the output conductances of transistors M
1
and M
2
. In fine line CMOS, the devices have high output conductances in saturation. Since the drain-source voltages of transistors M
1
and M
2
are different, an error is introduced. There is also sensitivity to supply voltage. As the value of the power supply voltage changes, the drain-source voltages of transistors M
1
and M
2
change differently, causing significant dependence of the set g
m
value on the power supply voltage.
An improvement on the circuit of
FIG. 1
is the prior art circuit shown in FIG.
2
. This is described in Eq. 2. This is equivalent to the arrangement of
FIG. 1
, except that the sources of transistors M
1
and M
2
are at the same potential (ground). Hence their thresholds are the same, and error due to different thresholds is eliminated. The problems with the prior art circuit of
FIG. 2
are as follows. In n-well technologies, the body terminal of n-channel devices is constrained to be grounded. Thus, this circuit can only be used to set the g
m
of grounded-source MOSFETs. This is a serious limitation. Another problem, which arises when the circuit of
FIG. 2
is used with short channel transistors, is that the MOSFET is no longer a square law device, and this causes significant error.
There is sensitivity to the output conductances of transistors M
1
and M
2
in FIG.
2
. In fine line CMOS, the devices have high output conductances in saturation. Since the drain-source voltages of transistors M
1
and M
2
are different, an error is introduced. Moreover, transistor M
1
can operate in the triode region if its threshold voltage is low. Thus, this arrangement can only be used for enhancement devices, or such g
m
values where transistor M
1
is not pushed into triode. There is also sensitivity to supply voltage. As the value of the power supply voltage changes, the drain-source voltages of transistors M
1
and M
2
change differently, causing significant dependence of the set g
m
value on the power supply voltage.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, the transconductance bias circuit includes: a differential pair having a first transistor and a second transistor; a resistor coupled between a gate of the first transistor and a gate of the second transistor, the gate of the first transistor is coupled to a reference voltage node; a third transistor coupled to the first transistor; a fourth transistor coupled to the second transistor; a fifth transistor coupled to the third transistor, a gate of the fifth transistor is coupled to the reference voltage node; a sixth transistor coupled to the fourth transistor, a gate of the sixth transistor is coupled to the reference voltage node; a current mirror coupled to the fifth and sixth transistor; and a seventh transistor coupled to the fourth transistor, a current in the seventh transistor is equal to a current in the resistor.


REFERENCES:
patent: 5602509 (1997-02-01), Kimura

Affiliated with

Also associated with

Rating

Fixed transconductance bias apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fixed transconductance bias apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fixed transconductance bias apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2963466