Fixed rate delay circuit

Details Fixed rate delay circuit Fixed rate delay circuit

1981-01-23

1983-08-23

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307602, 328 75, H03K 5135

Patent

active

044006667

ABSTRACT:
A binary number 2.sup.n can be divided at a rate 2.sup.m by means of shifting down successive digits thereof by m digits, n and m being positive integers which have a relation n>m therebetween. According to the above principle, successive digits of a binary number, which represents the number of clock pulses corresponding to an immediately preceding pulse interval of a pulse sequence having pulse intervals varied every moment, are shifted down by m digits. Thereafter, the coincidence between those shifted down successive digits and successive digits of a binary number which represents the number of clock pulses corresponding to a required fixed rate delay time is detected through plural exclusive OR gates, so as to find an instant to which the pulse sequence should be dalayed. As a result, the fixed rate delaying of the pulse sequence can be effected at the rate 1/2.sup.m of the immediately preceding pulse interval. This fixed rate delaying of the pulse sequence is particularly fit for the clock pulse reproduction in a digital VTR or a PCM recorder operating at varied speeds. The above fixed rate delaying of the pulse sequence can be efficiently employed for a digital frequency multiplier and a digital frequency differential discriminator.

REFERENCES:
patent: 3697879 (1972-10-01), Holliday
patent: 4011517 (1977-03-01), Pommerening et al.
patent: 4016495 (1977-04-01), Machanian
patent: 4068179 (1978-01-01), Sample et al.
patent: 4127823 (1978-11-01), Frost

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