Boots – shoes – and leggings
Patent
1994-07-27
1996-06-25
Gordon, Paul P.
Boots, shoes, and leggings
364748, G06F 738
Patent
active
055306624
ABSTRACT:
A fixed point signal processor includes a general register of "2n+.alpha."-bit width coupled to an arithmetic and logic unit (ALU) of "2n+.alpha."-bit width, a first data memory of "n"-bit width, and a first selection circuit for extending the "n"-bit width data to "2n+.alpha."-bit width to output the extended data to the general register. The first selection circuit selects continuous "n" bits from the "2n+.alpha."-bit width data held in the general register, to output the selected continuous "n" bits to the data memory. A second data memory receives the "2n+.alpha."-bit width data held in the general register for saving a plurality of items of "2n+.alpha."-bit width data, and a register indicates a head position of continuous "n" bits in the "2n+.alpha."-bit width data held in the second data memory. From the "2n+.alpha."-bit width data held in the second data memory, a second selection circuit selects continuous "n" bits starting from the head position, to output the selected continuous "n" bits to the general register. With this arrangement, a block floating processing is realized in hardware circuitry.
REFERENCES:
patent: 4872132 (1989-10-01), Retter
patent: 4876660 (1989-10-01), Owen et al.
patent: 4985861 (1991-01-01), Yamashina et al.
patent: 5031135 (1990-07-01), Patel et al.
patent: 5347480 (1994-09-01), Asghar et al.
patent: 5375079 (1994-12-01), Uramoto et al.
Gordon Paul P.
Moise Emmanuel L.
NEC Corporation
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