Fixed-point multiplier-accumulator architecture

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G06F 752

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active

048766607

ABSTRACT:
An integrated circuit multiplier-accumulator architecture includes an M-bit wide register for inputting an X operand and an N-bit wide input register for inputting a Y operand to a multiplier. The multiplier can selectably multiply or concatenate the operands to produce a binary product in the form of a first array of M+N parallel bits. A binary adder adds the binary product to a second array of M+N+P+1 parallel bits and outputs the sum as a Z result in the form of a third array of M+N+P+1 parallel bits. The Z result is stored in a selected one of two accumulators. A feedback path is provided to output selected accumulator contents to the adder as the second binary array of M+N+P+1 bits. Output ports are provided for outputting a selected portion of the accumulator contents. Preferably, the output ports can output the entire M+N+P bits in parallel, as well as any selected portion thereof. Overflow logic can be provided which determines from the (M+ n+P+1)th bit whether an overflow has occurred in the M+N+P bit result. A format adjust circuit is provided between the accumulators and the output ports for shifting the entire output accumulator contents a predetermined number of bits within a range of zero to at least P bits, and preferably P+1 bits, in the direction of the most significant bit.

REFERENCES:
patent: 4215416 (1980-07-01), Muramatsu
patent: 4546446 (1985-10-01), Machida
patent: 4700324 (1987-10-01), Dol et al.
Downing, P. et al., "Denser Process Gets the Most Out of Bipolar VLSI," Electronics, pp. 131-133, Jun. 28, 1984.
"A Bipolar Process That's Repelling CMOS," Electronics, pp. 45-47, Dec. 23, 1985.
"Surprise! ECL Runs on Only Microwatts," Electronics, pp. 35-38, Apr. 7, 1986.
Wilson, G., "Creating Low-Power Bipolar ECL at VLSI Densities," VLSI Systems Design, pp. 84-86, May, 1986.
Analog Devices, ADSP-1101 Enhanced Multiplier/Accumulator, Sep. 1984.
TRW, Inc., TMC2010 CMOS Multiplier-Accumulator, Nov. 1983.

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