Fixed-length delay generation circuit

Details Fixed-length delay generation circuit Fixed-length delay generation circuit

2001-11-16

2003-02-25

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S270000, C327S273000, C327S286000

Reexamination Certificate

active

06525585

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fixed-length delay generation circuit for delaying an input signal, and more particularly to a fixed-length delay generation circuit designed to restrain variations in delay values caused by, for example, temperature variations.
2. Description of the Related Art
As a kind of delay circuit, a fixed-length delay generation circuit that adds delay to a data signal or a similar signal and outputs it is incorporated into, for example, an optical disk device in order to adjust processing timings in a circuit provided at a rear stage. This kind of delay circuit is described, for example, in Japanese Published.Unexamined Patent Application No. Sho 63-46011.
FIG. 1
is a block diagram showing a structure of a conventional delay circuit described in the patent application No. Sho 63-46011. The conventional delay circuit described herein is provided with a ring oscillator
23
made up of an inverter IV
21
and a variable delay circuit
22
. The output terminal of the inverter IV
21
is connected to the input terminal of the variable delay circuit
22
, and the output terminal of the variable delay circuit
22
is connected to the input terminal of the inverter IV
21
. The variable delay circuit
22
includes a plurality of stages of variable delay units in which two inverters are connected in series with each other. The conventional delay circuit further includes a phase/frequency comparator
27
that compares the phase/frequency of an output signal of a reference frequency oscillator
24
that oscillates a fixed-frequency signal with the phase/frequency of an output signal of the ring oscillator
23
. The phase/frequency comparator
27
outputs a voltage (i.e., an analog signal) in accordance with a phase difference and a frequency. The conventional delay circuit further includes a variable delay circuit
21
that has the same structure as the variable delay circuit
22
and adds delay to, for example, a data input signal. A delay circuit control signal ctl, which is an output signal of the phase/frequency comparator
27
, is input to the variable delay circuits
21
and
22
.
In the thus constructed conventional delay circuit, a voltage that enlarges the on-resistance of the inverters that constitute the variable delay circuits
21
and
22
is output in the form of the delay circuit control signal ctl from the phase/frequency comparator
27
, when the frequency of the ring oscillator
23
is high, i.e., when a delay value is smaller than a predetermined value. For this reason, delay values in the variable delay circuits
21
and
22
increase. On the other hand, when the frequency of the ring oscillator
23
is low, a voltage that lowers the on-resistance of the inverters that constitute the variable delay circuits
21
and
22
is output in the form of the delay circuit control signal ctl from the phase/frequency comparator
27
. For this reason, delay values in the variable delay circuits
21
and
22
decrease. As a result, the frequency of the output signal of the ring oscillator
23
almost coincides with the frequency of the output signal of the reference frequency oscillator
24
, and the frequency of the output signal of the variable delay circuit
21
also stabilizes. The delay value in the variable delay circuit
21
at this time reaches half (½) of the frequency in the variable delay circuit
21
.
The patent application No. Sho 63-46011 further describes a delay circuit including a reference voltage source instead of the reference frequency oscillator. In this delay circuit, the frequency of an output signal from the ring oscillator is converted into a voltage, and this voltage is compared with a reference voltage of the reference voltage source, and, by feeding back the comparison result, a delay value is adjusted.
However, in the conventional delay circuit shown in
FIG. 1
, the delay value in the variable delay circuit
21
is intended to reach half the frequency of the output signal from the reference frequency oscillator
24
. Although the delay value in the ring oscillator
23
can be set at that value, a structural difference corresponding to the inverter IV
21
exists between the ring oscillator
23
and the variable delay circuit
21
. Therefore, disadvantageously, the delay value in the variable delay circuit
21
cannot be set at just half the frequency of the output signal from the reference frequency oscillator
24
. If the inverter IV
21
is removed from the ring oscillator
23
in order to overcome this disadvantage, the ring oscillator
23
will be made up of an even number of inverters, thereby making it impossible to activate the circuit.
Additionally, since the variable delay circuits
21
and
22
are constructed by connecting inverters in series, it is extremely difficult to increase the operating speed (i.e., subdivide a delay time unit) and, at the same time, widen the dynamic range. For example, let us suppose that minimum and maximum delay values per stage of a variable delay unit are “s” and “t”, respectively, and a variable delay circuit includes k stages of variable delay units. If so, a minimum delay value of this variable delay circuit is k×s, and a maximum delay value thereof is k×t. At this time, the minimum delay value k×s of the variable delay circuit is required to be made smaller, i.e., the number of stages k is required to be lessened, in order to increase the operating speed. However, a decrease in the number of stages k inevitably leads to a fall in the maximum delay value k×t, and therefore the dynamic range narrows. On the other hand, in order to widen the dynamic range, the number of stages k is required to be increased. However, an increase in the number of stages k leads to a rise in the minimum delay value: k×s, therefore leading to a fall in the maximum frequency of the ring oscillator
23
and to a fall in the operating speed.
Additionally, in most cases, the phase/frequency comparator
7
includes a charging-pump circuit in which a phase difference between two input signals is converted into a voltage through analog processing. Usually, the charging-pump circuit is provided with a P-channel transistor, an N-channel transistor, a resistance element, and a capacitive element. The variable delay unit is provided with a transistor that constitutes the inverter and adjusts a delay value such that the delay circuit control signal ctl is input to a gate so as to change on-resistance. Since many analog circuits are thus disposed in the conventional delay circuit shown in
FIG. 1
, another problem resides in that the conventional delay circuit is structurally liable to be influenced by manufacturing conditions and by temperature variations when used. Therefore, if the delay circuit is designed to become an integrated circuit (IC) having a high degree of integration, manufacturing variations and the like, will make it extremely difficult to obtain a desired operating condition.
Further, in the conventional delay circuit provided with the reference voltage source, since the reference voltage source is an analog circuit, the delay circuit is liable to be influenced by manufacturing conditions and by environmental changes when used, and it is extremely difficult to design a circuit capable of generating a reference voltage with high accuracy.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a fixed-length delay generation circuit capable of restraining a variation in delay values caused by manufacturing conditions and by environmental changes.
A fixed-length delay generation circuit according to the present invention comprises a first variable delay circuit, a clock generation circuit which generates a clock signal, a variable delay circuit group which includes one or more second variable delay circuits connected in series with each other, and a delay controller which controls delay in the first and second variable delay circuits. The second variable delay circuit generates a delay equal to a d

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