Fixed length data processing apparatus

Details Fixed length data processing apparatus Fixed length data processing apparatus

1999-03-29

2003-08-26

Voeltz, Emanuel Todd (Department: 2121)

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

C370S395100

Reexamination Certificate

active

06611871

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a fixed length data processing apparatus, in particular, to a fixed length data processing apparatus suitable for use to execute operation, administration and maintenance (OAM) of ATM (Asynchronous Transfer Mode) communication using fixed length data of 53 bytes called an ATM cell.
(2) Description of Related Art
ATM technique is being introduced for the purpose of realization of B-ISDN (Broadband aspect of ISDN) communication network so as to comply with high speed (large capacity) communications, variable bit rate communication for image, communication systems having various connection configurations such as point-to-point, point-to-n points (n is 2 or more), n points-to-n points, and the like, required presently.
For instance, in SDH (Synchronous Digital Hierarchy) transmission network [called SONET (Synchronous Optical Network) in North America], it is tried to map (store) signals for various communication services as ATM cells (fixed length data for asynchronous communication) onto a portion of payload of an SDH transmission frame [called STM (Synchronous Transfer Module), or STS (Synchronous Transport Signal) in SONET] and transmit the signal.
An ATM cell is mapped onto the transmission frame as above, a recent demand is to identify the ATM cell mapped onto the SDH transmission frame (hereinafter simply referred as a transmission frame, occasionally) as a unit and perform operation, administration and maintenance [a data (cell) processing such as a terminating processing on an OAM cell] even in the SDH transmission network.
In a ring network
1
′ configuring the SDH transmission network shown in
FIG. 48
, for example, it is necessary to interpose an ATM processing apparatus
4
′ for performing the above cell processing between SDH transmitting apparatus
2
′ and
3
′. Each of the SDH transmitting apparatus
2
′ and
3
′ is required to have a function of mapping an ATM cell on or taking out (demapping) an ATM cell from a transmission frame. Since the ring network
1
′ (SDH transmitting apparatus
2
′ and
3
′) accommodates a plurality of SDH transmitting apparatus
9
′-
1
through
9
′-n (n is an integer not less than 2) which become transmission points in a lower hierarchy, as shown in
FIG. 48
, the ATM cell processing apparatus
4
′i is required to perform the above cell processing on each transmission point.
In concrete, it is necessary to separately perform the above cell processing on each transmission frame in a lower order handled in each of the SDH transmission apparatus
9
′-
1
through
9
′-n [distinguished as an STS channel #i (i=1 through n) in each of the SDH transmitting apparatus
2
′ and
3
′ (in a transmission frame in a higher order)].
For this, each of the SDH transmitting apparatus
2
′ and
3
′ has mapping/demapping (MAP/DEMAP) units
2
′-
1
through
2
′-n and
3
′-
1
through
3
′-n according to the number of STS channels #i as shown in
FIG. 49
, for example. Each of the mapping/demapping units
2
′-
1
through
2
′-n and
3
′-
1
through
3
′-n includes a demapping unit
2
′d or
3
′d for taking out an ATM cell from a transmission frame in the upstream (UpStream) and or in the down stream (DownStream) and outputting the ATM cell to the ATM cell processing unit
4
′-i, and a mapping unit
2
′m or
3
′m for storing (mapping) an ATM cell from the ATM cell processing unit
4
′-i in a transmission frame in the upstream (UpStream) or in the downstream (DownStream) and outputting the ATM cell to another transmitting apparatus. The ATM processing apparatus
4
′ has ATM cell processing units (data processing units)
4
′-
1
through
4
′-n according to the number of the STS channels #i.
Each of the SDH transmitting apparatus
2
′ and
3
′ can thereby perform the above ATM cell mapping/demapping process for each STS channel #i by the mapping/demapping (MAP/DEMAP) units
2
′-
1
through
2
′-n and
3
′-
1
through
3
′-n. The ATM cell processing unit
4
′-i can perform the above cell processing for each STS channel #i.
Namely, the ATM processing apparatus
4
′ performs the cell processing on ATM cells in transmission frames handled by each of the SDH transmitting apparatus
9
′-
1
through
9
′-n separately for each STS channel #i by each exclusive ATM cell processing unit
4
′-i serially.
For instance, an ATM cell from the SDH transmitting apparatus
9
′-
1
,
9
′-
2
, . . . or
9
′-n in the lower hierarchy of the SDH transmitting apparatus
3
′ is taken out from a transmission frame in the mapping/demapping unit
3
′-
1
,
3
′-
2
, . . . or
3
′-n corresponding to the STS channel #i, and sent to a corresponding ATM cell processing unit
4
′-i according to an internal reference cell cycle of the ATM processing apparatus
4
′.
The ATM cell undergoes the cell processing in the ATM cell processing unit
4
′-i corresponding to the STS channel #i is mapped on a transmission frame in the corresponding mapping unit
2
′-
1
,
2
′-
2
, . . . or
2
′-n, and transmitted to the SDH transmitting apparatus
9
′-
1
,
9
′-
2
, . . . or
9
′-n accommodated in the lower hierarchy of the SDH transmitting apparatus
2
′.
Each of the ATM cell processing units
4
′-i identifies an ATM cell, and executes fault management [termination of an AIS (Alarm Indication Signal) or an RDI (Remote Defect Indication) cell] on an ALM (Alarm) cell of an OAM cell, mainly.
For instance, when the ATM processing apparatus
4
′ receives an OAM (ALM) cell (VP/VC-AIS) indicating occurrence of a trouble within a certain VP/VC connection, the ATM processing apparatus
4
′ notifies of a similar AIS the downstream, or when receiving an alarm (SONET alarm or the like) in a higher order than AIS, the ATM processing apparatus
4
′ generates a VP/VC-AIS/RDI cell and sends the cell to a desired destination.
For this, each of the ATM cell processing unit
4
′-i has, as shown in
FIG. 49
, for example, a cell identifying unit
4
′a, a cell generating unit
4
′b, a cell inserting unit
4
′c for downstream, a cell inserting unit
4
′ d for upstream, and a microcomputer I/F unit
4
′e.
The cell generating unit
4
′b generates an ALM cell (VP-AIS, VC-AIS), and sends the cell to the downstream through the DnS cell inserting unit
4
′c. On the other hand, an ALM cell (VP-RDI, VC-RDI) in the opposite direction is sent to the upstream through the UpS cell inserting unit
4
′d.
The microcomputer I/F unit
4
′e has an interface to set an operation channel, operation environments and the like from a system CPU or collect maintenance and management information (ALM information and the like).
The ATM cell or the like outputted from the ATM cell processing unit
4
′-
1
,
4
′-
2
, . . . , or
4
′-i is again mapped on a transmission frame in the mapping/demapping unit
2
′-
1
,
2
′-
2
, . . . or
2
′-n, and receives by another apparatus which is a destination of the ALM cell.
The cell identifying unit
4
′a in the above ATM cell processing unit
4
′-
1
holds information for identifying a cell of an OAM (ALM) cell (VP/VC-AIS) to identify a receive cell by comparing the received cell with the information. However, if the apparatus holds the identification information for each channel [virtual channel (VP/VC) in ATM communication], the apparatus has to hold the identification information for 1024 channels in one STS channel, for example, which leads to an increase in scale of the apparatus.
If a network configuration (connection configurati

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