Boots – shoes – and leggings
Patent
1994-03-28
1997-10-21
Shah, Alpesh M.
Boots, shoes, and leggings
39520002, 364229, 3642382, 36424294, 364DIG1, G06F 1300
Patent
active
056806345
ABSTRACT:
A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addressable configurations. The modular, polymorphic interconnect further permits allocation and deallocation of selected electronically reconfigurable devices for a particular logically addressable configuration. The modular, polymorphic interconnect additionally permits the logical topology of selected electronically reconfigurable devices to be configured as at least one mixed-radix, N-dimensional network. The logical topology of mixed-radix, N-dimensional networks can be dynamically changed under control for a new configuration of logical addresses for selected electronically reconfigurable devices. The modular, polymorphic interconnect also permits one or more electronically reconfigurable devices to be selected from at least one logically related set of electronically reconfigurable devices, making the resulting network system particularly well suited for a variety of purposes related to resource management.
REFERENCES:
patent: 3408532 (1965-10-01), Hultberg et al.
patent: 3609397 (1971-09-01), Zaman
patent: 4272829 (1981-06-01), Schmidt et al.
patent: 4605928 (1986-08-01), Georgiou
patent: 4630045 (1986-12-01), Georgiou
patent: 4679186 (1987-07-01), Lea
patent: 4744026 (1988-05-01), Vanderbei
patent: 4744027 (1988-05-01), Bayer et al.
patent: 4744028 (1988-05-01), Karmarkar
patent: 4745630 (1988-05-01), Underwood
patent: 4888692 (1989-12-01), Gupta et al.
patent: 4943909 (1990-07-01), Huang
patent: 5020059 (1991-05-01), Gorin et al.
patent: 5030921 (1991-07-01), Kane
patent: 5036473 (1991-07-01), Butts et al.
patent: 5038386 (1991-08-01), Li
patent: 5075595 (1991-12-01), Kane
patent: 5182466 (1993-01-01), Ohkubo
patent: 5289365 (1994-02-01), Caldwell
Chen and Shin, "Processor Allocation in an N-Cube Multiprocessor Using Gray Codes," IEEE Transactions on Computers, Dec. 1987, pp. 1396-1407.
Chen and Shin, "Subcube Allocation and Task Migration in Hypercube Multiprocessors," IEEE Transactions on Computers, Sep. 1990, pp. 1146-1155.
Bhuyan, Laxmi and Agrawal, Dharma, "Generalized Hypercubes and Hyperbus Structures for a Computer Network", IEEE Transaction on Computers, Apr. 1984, pp. 323-333.
Goede, W.F., "A Digitally Addressed Flat-Panel CRT," IEEE Transactions on Electronic Devices, Nov. 1973, pp. 378-387.
Katai, A.H., "Three-and Four-Dimensional Addressing of Flat-Panel Displays," Proceedings of the SID, vol. 27/4, 1986, pp. 309-312.
Larar, Jerry N., et al., "Vector Quantization of the Articulatory Space," IEEE Transactions on Acoustics, Speech and Signal Processing, Dec. 1988, pp. 1812-1818.
Gilbert, E.N. and Moore, E.F., "Variable-Length Binary Encoding," The Bell System Technical Journal, Jul. 1959, pp. 933-967.
Smith, K.C., "The Prospects for Multivalued Logic: A Technology and Applications View," IEEE Transactions on Computers, Sep. 1981, pp. 619-634.
"Data Flow Computers and VLSI Computations," Computer Architecture and Parallel Processing, Chapter 10, pp. 732-811.
Trimberger, Stephen, ed., Field-Progammable Gate Array Technology (Boston: Kluwer Academic Publishers, 1994), pp. 1-9, 218-223.
Hilbess, Peter A.J., Processor Networks and Aspects of the Mapping Problem (Cambridge University Press, 1991), pp. 1-3, 65-77.
Chiou, Arthur, "Photorefractive Optical Interconnects", Jahns and Lee, eds., Optical Computing Hardware (Academic Press, Inc., 1994), Chapter 10, pp. 249-285.
Murdocca, Miles, A Digital Design Methodology for Optical Computing (Cambridge: The MIT Press, 1990), Chapter 4, pp. 43-98.
Wells, Mark B., "Aspects of Language Design for Combinatorial Computing," IEEE Transactions on Electronic Computers, Aug. 1964, pp. 431-438.
Newell, Allen, "On Programming a Highly Parallel Machine to be an Intelligent Technician," Proceedings of the Western Joint Computer Conference, IRE-AIEE-ACM, 1960, pp. 267-282.
Siegel, Howard J., et al., "A Survey of Interconnection Methods for Reconfigurable Parallel Processing Systems," National Computer Conference, 1979, pp. 529-542.
Sztipanovits, Janos, "Toward Structural Adaptivity," IEEE 1988, pp. 2359-2366.
Kartashev, Steven and Kartashev, Svetlana, "Problems of Designing Supersystems with Dynamic Architectures," IEEE Transactions on Computers, Dec. 1980, pp. 1114-1132.
French, P.C. and Taylor, R.W., "A Self-Configuring Processor," IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 5-7, 1993.
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