Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1998-07-14
2001-09-25
Pham, Chi (Department: 2631)
Pulse or digital communications
Receivers
Angle modulation
Reexamination Certificate
active
06295325
ABSTRACT:
This application is similar to the following co-pending U.S. patent applications, all of which are expressly incorporated herein by reference:
U.S. patent application Ser. No.60/055,694, entitled “Variable Baudrate Demodulator”, filed Jul. 15, 1997;
U.S. Pat. No. 6,081,565 allowed on Jun. 27, 2000 entitled “Amplitude Based Course Automatic Gain Control Circuit”, filed Jul. 15, 1997;
U.S. patent application Ser. No. 09/019,402, entitled “Power Based Digital Automatic Gain Control Circuit”, filed Jul. 15, 1997;
U.S. Pat. No. 6,108,375 allowed on Aug. 22, 2000 entitled “Equalization Circuit for Unknown QAM Constellation Size”, filed Jul. 15, 1997;
U.S. patent application Ser. No. 60/052,572, entitled “Fixed Clock Based Arbitrary Symbol Rate Timing Recovery Loop”, filed Jul. 15, 1997;
U.S. Pat. No. 6,081,565 allowed on Jun. 27, 2000 entitled “Fixed Clock Based Arbitrary Symbol Rate Timing Recovery Loop”, filed Jul. 15, 1997;
U.S. patent application Ser. No. 60/052,572, entitled “Amplitude Based Coarse AGC”, filed Jul. 15, 1997;
U.S. patent application Ser. No. 5,963,594 entitled “Vector Tracking Filter”, filed Dec. 31, 1996;
U.S. Pat. No. 5,870,442 allowed on Nov. 5, 1999 entitled “Variable Baudrate Demodulator”, filed Dec. 31, 1996; and
U.S. patent application Ser. No. 09/114,948, entitled “Variable Baud Rate Demodulator”, co-filed on even date herewith.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to timing of a received data stream. More particularly, it relates to a data signal timing recovery loop useful for establishing the symbol rate of an arbitrary received data signal using a fixed sampling clock.
2. Background of Related Art
High speed data transmission systems, e.g., modems, operate in general by modulating a high frequency carrier corresponding to a desired channel with a low frequency data signal of fixed baud rate. The modulated data signal is transmitted to a receiver, which demodulates the received high frequency modulated signal to recover the transmitted digital symbols at the far transmitter baud rate.
In such data transmission systems, the baud rate of the transmitting and receiving devices are generally fixed at a discrete level, and generally include a modulator and/or demodulator which operates at a fixed baud rate. Any fine adjustments which might be made in the baud rate of the receiver are typically made in the sampling rate of an analog-to-digital (A/D) converter sampling the incoming analog signal. However, these conventional baud rate adjustments are limited to just a few hundreds or thousands of parts per million of the baud rate, and are not able to adjust through a wide range of baud rates without requiring additional and/or different filtering for each different baud rate. The need for additional and/or different filtering for each received baud rate is cumbersome and expensive to implement. Moreover, different receivers must be developed and manufactured for each expected baud rate.
There is a need for a data signal timing recovery loop operating on fixed clock rate (fs) digital samples of arbitrary baud rate data signals to produce digital samples streams synchronous to the baud rate of the arbitrary baud rate received data signal.
SUMMARY OF THE INVENTION
In accordance with the disclosed embodiments, a quadrature amplitude modulated (QAM) data signal timing recovery loop comprises a received data signal baud event estimator adapted to produce an fs sampling time offset value adjustment based on a statistical baud tone phase error estimate and a nominal received data signal baud rate parameter set at receiver startup time. Two continuously variable digital delay elements (CVDD) respond to the fs sampling time offset value producing interpolated samples at the appropriate rate based upon sets of closes neighbor samples in time of the received data signal, collected at the fixed A/D sampling rate, fs. The production rate of the interpolated sample stream is exactly equal to a system-programmed multiple of the actual received data signal baud rate.
In accordance with another aspect of the present invention, a timing recovery loop comprises a filter adapted to receive In-Phase and Quadrature components of a received signal and to provide filtering to produce filtered In-Phase components and filtered Quadrature components. Two complex value squarers are adapted to receive quadrature band edge filtered In-Phase and Quadrature components and produce first and second complex value squared outputs. Each of the two complex value streams produced contains a statistical discrete tone (complex phasor) of frequency precisely equal to the received data signal baud rate, among other unwanted energy artifacts. The two complex streams are added to cancel unwanted energy artifacts that reside in each individual complex stream due to any residual carrier frequency offset that may exist in the nominal carrier frequency demodulated received data signal. A de-rotating integrator is adapted to receive and de-rotate the first and second squared outputs, and to accumulate a squared complex signal. This de-rotating integrator demodulates and low pass filters the statistical baud tone phasor contained in the summed complex stream described above. A phase estimator is adapted to receive the demodulated and low pass filtered complex-valued baud tone and to generate a received data signal baud event phase error estimate. A phase locked loop is adapted to receive and track this phase error estimate, and an fs sampling time offset calculator is coupled to the output of the phase locked loop. The fs sampling time offset calculator outputs a fs sampling time offset value based upon the fs sampling time offset adjustment produced by the phase locked loop and a nominal received data signal baud rate parameter set at receiver startup time.
A demodulator in accordance with the principles of the present invention comprises an analog-to-digital converter adapted to receive an analog signal and produce digital samples at a first, fixed frequency fs. A digital demodulator is adapted to receive the digital samples and separate the digital samples into In-Phase and Quadrature components. The digital demodulator produces samples at the first frequency fs rate. Two continuously variable digital delay (CVDD) devices adjust the rate of representations of the In-Phase and Quadrature components to produce rate adjusted components at a second frequency. A decimator is adapted to decimate the rate adjusted components to produce decimated components at a third frequency, and a timing recovery loop feedback element is adapted to generate a fs sampling time offset value adjustment which is provided to an fs sampling time offset calculator that manages a pair of continuously variable interpolator/decimator elements.
A method of adjusting the output rate of the pair of continuously variable interpolator/decimator elements in accordance with the principles of the present invention comprises calculating an fs sampling time value adjustment based on an analysis of In-Phase components and Quadrature components corresponding to quadrature amplitude modulated samples, and calculating fs sampling time offset values and manufacturing continuously variable interpolator/decimator output events based upon the fs sampling time offset adjustment produced by the phase lock loop and a nominal received data signal baud rate parameter set at receiver startup time.
REFERENCES:
patent: 4755761 (1988-07-01), Ray Jr.
patent: 4866647 (1989-09-01), Farrow
patent: 5495203 (1996-02-01), Harp et al.
patent: 6005640 (1999-12-01), Strolle et al.
C.W. Farrow, “A Continuously Variable Digital Delay Element”, IEEE, 1988, pp. 2641-2645.
Tony Kirke, “Interpolation, Resampling, and Structures for Digital Receivers”, Communication Systems Design, Jul. 1998, pp. 43-49.
Farrow Cecil William
Marandi Vahid
Mobin Mohammad Shafiul
Mondal Kaylan
Udovic Daniel J.
Agere Systems Guardian Corp.
Bollman William H.
Burd Kevin M.
Pham Chi
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