Five-volt tolerant differential receiver

Details Five-volt tolerant differential receiver Five-volt tolerant differential receiver

1991-06-28

1992-12-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072965, 307448, 307451, 307497, H03K 190175, H03K 1970

Patent

active

051720167

ABSTRACT:
A differential, CMOS receiver includes a transistor, coupled in parallel with an input transistor, which limits voltage differentials across an input transistor. A corresponding, similarly sized transistor balances current loading in a differential transistor. The transistor in parallel with the input transistor, whose drain is coupled directly to the power supply, quickly pulls the input transistor source and drain up to power supply voltage on an input transient from logical zero to a logical one which exceeds the power supply voltage. Another transistor coupled between the output node and the power supply rail defeats differential amplifier action when the input voltage is high out of its normal range.

REFERENCES:
patent: 4698526 (1987-10-01), Allan
patent: 4724344 (1988-02-01), Watanabe
patent: 4825110 (1989-04-01), Yamaguchi et al.
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 4929853 (1990-05-01), Kim et al.
patent: 4965469 (1990-10-01), Kondoh et al.
patent: 4999529 (1991-03-01), Morgan, Jr. et al.

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