Patent
1997-07-09
1998-07-14
Ellis, Richard L.
395876, 395873, 395309, 395310, 395552, G06F 1202
Patent
active
057818029
ABSTRACT:
This is an improved FIFO controller which is capable of buffering data between systems which are asynchronous relative to one another and is free of false flags and internal metastability. The FIFO controller comprises a controller means for receiving read/write data strobes and for generating an initial read/write pointer and a next read/write pointer. Memory means are coupled to the controller means for storing the read/write pointer and read/write data information. Flag generation means are coupled to the controller means for computing a status of the FIFO flags and for preventing momentary false flags.
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Ellis Richard L.
Moy Jeffrey D.
Patel Gautam R.
VLSI Technology Inc.
Weiss Harry M.
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