Communications: electrical – Digital comparator systems
Patent
1974-11-13
1976-11-16
Shaw, Gareth D.
Communications: electrical
Digital comparator systems
340173RC, G11C 1900, G11C 2100
Patent
active
039926990
ABSTRACT:
A first-in/first-out memory device has a shift register with a storage capacity of n stages in which data units can be stored, and a modulo-n address counter having one state representing each stage of the shift register. In one embodiment designed for fast data storage, a data unit is transferred to the input of the shift register, during a write mode, and the state of the address counter is advanced for each data unit so transferred; during a read mode, data units are recirculated from the output of the shift register to its input, the shift register is shifted n times, the state of the address counter is advanced n - 1 times, and the data unit appearing at the output of the shift register when the address counter state represents an empty shift register is retrieved. In another embodiment designed for fast data retrieval, a data unit is retrieved from the output of the shift register during a read mode and the state of the address counter is advanced for each data unit so transferred; during a write mode, data units are recirculated from the output of the shift register to its input, the shift register is shifted n times, the state of the address counter is advanced n - 1 times, and a data unit is stored in the input of the shift register when the address counter state represents a full shift register.
REFERENCES:
patent: 3501746 (1970-03-01), Vosbury
patent: 3611303 (1971-10-01), Serracchioli
patent: 3636519 (1972-01-01), Heath
patent: 3742466 (1973-06-01), Hamm
patent: 3755788 (1973-08-01), Finch
patent: 3760382 (1973-09-01), Itoh
patent: 3771140 (1973-11-01), Tromp
patent: 3829843 (1974-08-01), Cichetti, Jr.
Communication Mfg. Co.
Shaw Gareth D.
Thomas James D.
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