Firmware controlled transmit datapath for high-speed packet swit

Details Firmware controlled transmit datapath for high-speed packet swit Firmware controlled transmit datapath for high-speed packet swit

1998-04-28

2000-12-19

Olms, Douglas W.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370395, 370389, H04L 1256

Patent

active

061635391

ABSTRACT:
A datapath packet transmission controller which includes a central processing unit (CPU), a transmit FIFO buffer operative to receive and temporarily store data packets, and a disposition FIFO buffer coupled to said CPU for holding packet disposition commands received from said CPU. The CPU controls reception and storage of data packets in the transmit FIFO buffer, accesses data in data packets in the transmit FIFO buffer, provides disposition commands which control the disposition of packets after storage in the transmit FIFO buffer.

REFERENCES:
patent: 5557610 (1996-09-01), Calamvokis et al.
patent: 5799014 (1998-08-01), Kozaki et al.
patent: 5872783 (1999-02-01), Chin
patent: 5898687 (1999-04-01), Harriman et al.
patent: 5903560 (1999-04-01), Samejim et al.
patent: 6009078 (1999-12-01), Sato

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