Fir filter architecture with precise timing acquisition

Details Fir filter architecture with precise timing acquisition Fir filter architecture with precise timing acquisition

1995-01-04

2000-02-29

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

708316, 708319, G06G 702, G06F 1710

Patent

active

060321717

ABSTRACT:
A novel Finite Impulse Response ("FIR") filter (10)" is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

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Richard G. Yamasaki, et al., "A 72Mb/S PRML Disk-Drive Channel Chip with an Analog Sampled Data Signal Processor", ISSCC94/Session 17/Disk-Drive Electronics/Paper FA 17.2, 1994 IEEE International Solid-State Circuits Conference, pp. 278, 279.
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