FIR filter architecture for 100Base-TX receiver

Details FIR filter architecture for 100Base-TX receiver FIR filter architecture for 100Base-TX receiver

2000-07-13

2003-09-02

Tran, Khai (Department: 2631)

Pulse or digital communications

Equalizers

Automatic

C375S350000

Reexamination Certificate

active

06614842

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to receivers for decoding 100Base-TX signals, and in particular to a receiver employing a finite impulse response (FIR) filter for adaptive equalization and automatic gain control.
2. Description of Related Art
The IEEE 802.3 (“Ethernet”) standard defining a digital media interface commonly used for transmitting data between computers linked through a network includes a “100Base-TX” protocol for category 5 (CAT5) twisted-pair data transmission employing MLT-3 line encoding.
FIG. 1
is a timing diagram illustrating how data is represented by an “ideal” MLT-3 encoded waveform. The MLT-3 waveform is organized into a sequence of 8 ns (nanosecond) data cycles and conveys data at a rate of 125 Mb/s (megabits per second), one bit of data per data cycle. The MLT-3 standard defines three voltage levels referenced as +1, 0 and −1. During each cycle the waveform may stay at the same level, or may transition from level +1 to level 0, from level 0 to level −1, from level −1 to level 0, or from level 0 to level +1. When the waveform does not transition between levels during a current (Kth) data cycle, it represents the same data value as it represented during the preceding (K−1)th data cycle. When the waveform transitions during the Kth data cycle, it represents a bit of state opposite to that of bit represented during the preceding (K−1)th data cycle.
As the MLT-3 waveform travels over a network it can be distorted in ways that can make it difficult for a receiver to extract the data conveyed by the waveform. Communication channels conveying the MLT-3 waveform include magnetic modules coupling the waveform onto the twisted pair cable. Since these modules act like high pass filters, they attenuate low frequency components of the waveform. Thus when an MLT-3 waveform has relatively few transitions during a relatively long period, it appears as a low frequency signal, and the magnetic modules cause the waveform to suffer a type of distortion called “baseline wander” as illustrated in FIG.
2
. The twisted pair conveying an MLT-3 waveform also has an insertion loss and a frequency-dependent attenuation that can further distort the waveform, for example as illustrated in FIG.
3
. To avoid errors in decoding an MLT-3 waveform, a 100Base-TX receiver should provide baseline wander correction, gain control compensation for insertion loss and equalization for frequency-dependent attenuation of the twisted pair.
The paper entitled “A CMOS Transceiver for 10 Mb/s and 100 Mb/s Ethernet”, by Everitt et al, published December 1998 in the IEEE Journal of Solid-State Circuits, Vol 33, No 12, describes a receiver illustrated herein in FIG.
4
. An attenuator
12
attenuates the input MLT-3 signal to prevent clipping. A summer
14
adds the output of a baseline compensation circuit is to the output of attenuator
12
to level shift the MLT-3 signal as necessary to compensate for any base line wander. A high-pass filter
18
having adjustable frequency response characteristics filters the output of summer
14
to provide equalization, and an automatic gain control (AGC) circuit
20
amplifies the output of summer
14
to compensate for insertion loss. A summer
22
sums the outputs of high-pass filter is and AGC
20
to supply an equalized and compensated MLT-3 signal to a low-pass filter
24
which filters high frequency noise out of the signal.
A three-level clock-recovery slice circuit
26
, phase-locked loop circuit
28
and 180 degree phase shifter
30
process the waveform output of low pass filter
24
to produce a 125 Mhz clock signal (CLOCK) phase locked to the MLT-3 waveform. The CLOCK signal clocks a six-level bit slice circuit
32
which produces data representing the voltage of the MLT-3 waveform output of low pass filter
24
as one of six levels. Other circuits (not shown) recover the transmitted data from the output data of slice circuit
32
. The data output of slice circuit
32
also provides input to a digital logic circuit
34
which processes that data to control the amount compensation to be provided by baseline wander compensation circuit
16
and AGC circuit
20
and to adjust high pass filter
18
as needed to compensate for frequency-dependent attenuation.
With a high component count, the receiver requires substantial power and die area. What is needed is a 100Base-TX receiver having lower power and die area requirements.
SUMMARY OF THE INVENTION
A 100Base-TX Receiver in accordance with the invention employs a finite impulse response (FIR) filter to provide both equalization and insertion loss compensation for an MLT-3 input signal.
The FIR filter includes three delay stages, each delaying the input signal with an 8 ns delay (the period of one data cycle of the MLT-3 input signal), a set of three amplifiers for amplifying the delay stage outputs with gains C
1
, C
2
and C
3
, and a summer for summing the outputs of the three amplifiers to produce a compensated, equalized MLT-3 signal. The receiver also includes a low-pass filter for filtering high frequency noise out of the FIR filter output signal.
A data slicer digitizes the low-pass filter's output MLT-3 signal during each data cycle to produce slice data representing that MLT-3 signal as being within one of six levels. An adaptive control signal processes the slice data to adaptively adjust the gains C
1
, C
2
and C
3
of the three FIR amplifiers to provide a correct amount of equalization and insertion loss compensation.
The adaptive control circuit also processes the slice data to adaptively adjust the phase of a clock signal controlling timing of the data slicer, to adaptively adjust an amount of baseline wander compensation provided to the MLT-3 input signal, and to produce an output digital signal representing the data sequence conveyed by the MLT-3 input signal.
The use of an FIR filter to provide equalization and compensation reduces the amount of area on an integrated circuit die needed to implement a 100Base-TX receiver and allows the receiver to operate with less power than prior art 100Base-TX receivers.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.


REFERENCES:
patent: 5822423 (1998-10-01), Jehnert et al.
patent: 6047026 (2000-04-01), Chao et al.
Shoval, Ayal; Omid Shoaei; Kathleen O. Lee and Robert H. Leonowich, “A CMOS Mixed-Signal 100Mb/s Receive Architecture for Fast Ethernet,” IEEE 1998 Custom Integrated Circuits Conference, pp. 253-256.
Everitt, James; James F. Parker; Paul Hurst; Dave Nack and Kishan Rao Konda, “A CMOS Transceiver for 10-Mb/s and 100-Mb/s Ethernet,” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 2169-2177.
Shoaei, Omid; Ayal Shoval and Robert Leonowich, “A 3V Low-Power 0-25 &mgr;m CMOS 100Mb/s Receiver for Fast Ethernet,” International Solid-State Circuit Conference 2000/Session 18/Wireline Communications/Paper WA 18.4, pp. 308-309.
Kelly, N. Patrick; Daniel L. Ray and David W. Vogel, “A Mixed-Signal DFE/FFE Receiver for 100Base-TX Applications,” International Solid-State Circuit Conference 2000/Sessuib 18/Wireline Communications/Paper WA 18.5, pp. 310-311.

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