Fir filter and ramp-up/-down control circuit using the same

Details Fir filter and ramp-up/-down control circuit using the same Fir filter and ramp-up/-down control circuit using the same

2006-08-29

2006-08-29

Chaki, Kakali (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07099907

ABSTRACT:
An n-bit shift register102for shifting input data through successive bit stages and AND gates103-i(i being 1 to n) corresponding to the bit stages of the shift register102are provided. A control circuit101feeds out control signals107-ifor on-off controlling the feeding of the outputs of the corresponding bit stages of the shift register102. Multipliers104-imultiply the on-off controlled data and predetermined filter coefficient data, and an adder circuit105adds together the output of the multipliers to derive an FIR filter output including ramp-up and -down. A ramp-up/-down signal is fed to a shift register in the control circuit101, and ramp-up data is derived from the output of the adder circuit105. Thus, the circuit can be readily constructed without scale increase.

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