Finite state machine with minimized vector processing

Details Finite state machine with minimized vector processing Finite state machine with minimized vector processing

1993-12-28

1995-10-17

Lall, Parshotam S.

395800, G06F 930

Patent

active

054598419

ABSTRACT:
Conventional AND vectors are compared to corresponding input vectors of the same length as part of the logic processing associated with the finite state machine. AND vectors having a single set bit are translated into AND index vectors in which the bit position of the single set bit is encoded. AND index vectors are also identified by an index flag. The encoded bit position is utilized to identify the corresponding bit position in the input vector to perform a TRUE/FALSE test to determine an overall TRUE or FALSE indication. This technique avoids a bit by bit comparison for AND vectors having a single set bit.

REFERENCES:
patent: 4101967 (1978-07-01), Hajduk
patent: 4212076 (1980-07-01), Conners
patent: 4399377 (1983-08-01), Jones
patent: 5245339 (1993-09-01), Cideciyan
patent: 5300931 (1994-04-01), Lindsay et al.
patent: 5301100 (1994-04-01), Wagner
patent: 5317757 (1994-05-01), Medicke et al.

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