Finite impulse response filter and method

Details Finite impulse response filter and method Finite impulse response filter and method

1999-02-16

2001-08-14

Ngo, Chuong Dinh (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S714000

Reexamination Certificate

active

06275835

ABSTRACT:

FIELD OF THE INVENTION
The invention concerns an apparatus and method for a finite impulse response (FIR) filter.
BACKGROUND OF THE INVENTION
Data can be filtered by multiplying it by a series of coefficients, and summing the result. Usually, a filtering process involves many multiplication. Both data and coefficients are stored in memory banks and the filtering results in many accesses to these memory banks.
Both data and coefficients can be full complex numbers, pure real or pure imaginary numbers. Usually, filtering is done in several modes, depending on the type of data and coefficients. For example:
a. Multiplying pure real or pure imaginary coefficients by pure real or pure imaginary data.
b. Multiplying pure real or pure imaginary coefficient by complex data.
c. Multiplying alternating pure real and pure imaginary coefficients by complex data.
d. Multiplying complex coefficients by complex data.
Usually, coefficient vectors, having coefficient elements, are stored in a coefficient memory bank (CMB), and data vectors, having data elements, are stored in data memory bank (DMB). The successive elements of a data vector are usually stored in consecutive memory words within the DMB. The successive elements of a coefficient vector are usually stored in consecutive memory words within the CMB.
If data vector elements or coefficient vector elements have both real values (DR(i) denotes a real element of the data vector, CR(i) denotes a real element of the coefficient vector) and imaginary values (DI(i) denotes an imaginary element of the data vector, CI(i) denotes a imaginary element of the coefficient vector), the real value of an element is usually stored before the imaginary value of the same element.
For example, if a data vector is complex it is stored in the DMB in the following order: DR(
0
), DI(
0
), DR(
1
), DI(
1
). If the data vector is pure real it is stored in the following order: DR(
0
), DR(
1
), DR(
2
) . . . If the coefficient vector is complex it can be stored in two different ways. The first is: CR(
0
), CI(
0
), CR(
1
), CI(
1
) . . . . The second is: CR(N−1), CI(N−1), CR(N−2), CI(N−2). If the coefficient vector is pure real it can be stored in two different ways. The first is: CR(
0
), CR(
1
), CR(
2
) . . . . The second is: CR(N−1), CR(N−2), CR(N−3).
FIG. 1
is a simplified schematic diagram of address generator
107
according to the prior art. Address generator
107
includes: M-bit counter
109
, having input
108
and M outputs
110
-
118
; M multiplexers
120
-
128
, having first set of M data inputs
130
-
138
, second set of M data inputs
140
-
148
, M control inputs
150
-
158
and M outputs
160
-
168
; Logic XOR gate (i.e.—XOR)
170
, having two inputs
172
,
174
and one output
176
. M+1=Log
2
L, wherein L is the length of DMB (i.e.—the number of memory words of the DMB).
First set of M data inputs (i.e.—first inputs)
130
-
138
of M multiplexers
120
-
128
are coupled to M outputs
110
-
118
of M-bit counter (i.e.—counter)
109
. M−1 second data outputs
140
-
146
of multiplexers
120
-
126
are coupled to M−1 outputs
112
-
118
of counter
109
, so that the i'th output of counter
109
(where i is an index having values of 1 to M−1) is coupled to the second data input of the (i+1)'th multiplexer.
For example, second output
112
of counter
109
is coupled to the second data input
140
of the first multiplexer
120
. (M−1)'th output
118
of counter
109
is coupled to second data input
146
of the (M−1)'th multiplexer
126
. Second data input
148
of the M'th multiplexer
128
is coupled to constant “0”. Input
174
of XOR
170
is coupled to first output
110
of counter
109
.
Input signal “Im”
180
, from a control unit (not shown in
FIG. 1
) is sent to input
174
of XOR
170
. Input signal “double”
182
, sent by the control unit is inputted to M control inputs
150
-
158
of M multiplexers
120
-
128
. Double
182
indicates that a data vector stored within the DMB (not shown in
FIG. 1
) is complex and that coefficient vector, stored in the CMB (not shown in
FIG. 1
) is pure real or pure imaginary, or has alternating pure real and pure imaginary elements. Im
180
indicates that a real value element is fetched from one memory data bank and a imaginary value elements is fetched simultaneously from the other memory bank. Input signal FIR
184
is sent to input
108
of counter
109
. FIR
184
indicates, for example, that there is a need to generate a new address, or that there is need to read a new data word.
Output signal
185
of address generator
107
(i.e.—the address word) is provided by the signals on outputs
160
-
168
of M multiplexers
120
-
128
and the signal on output
176
of XOR
170
. The least significant bit of the address word equals the signal from output
176
of XOR
170
. The remaining M bits of the address word are presented by the output signals from M outputs
160
-
168
of M multiplexers
120
-
128
. The (i+1)'th bit (where i has values from 1 to M) of the address word, is the output signal from the output of the i'th multiplexer. For example the second bit of the address word is the signal from output
160
of first multiplexer
120
. The (M+1)'th bit of the address word equals the output signal from output
168
of M'th multiplexer
128
.
The delay time of the address generator
107
equals the delay time of the M'th output bit of counter
109
(i.e.—the time for the M'th output
118
of counter
109
to change as result of an input signal at input
108
of counter
109
) plus the delay time of a multiplexer (one out of
120
-
128
).
A significant disadvantage of this and other prior art arrangements is the complicated address generator, needed to support the accesses to data vector stored in DMB. The complexity of the address generator is a result of the different ways in which data and coefficient are stored within the DMB and the CMB. Another disadvantage of the prior art is a large delay time, caused by the complex address generator. The large delay time limits the working frequency of the FIR filter.
For the above mentioned reasons and for other reasons, there continues to be a need for an improved FIR filter and method.


REFERENCES:
patent: 5179530 (1993-01-01), Genusov et al.

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