Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-05-28
2002-12-31
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S120000
Reexamination Certificate
active
06501408
ABSTRACT:
The present invention relates in general to a finite impulse response digital-to-analog converter, hereinafter referred to as FIRDAC.
The finite impulse response principle for a digital-to-analog converter is known per se, and described for instance in U.S. Pat. No. 5,323,157. Generally speaking, a FIRDAC comprises a shift register with a large number of stages, typically more than hundred stages, which receives a bitstream input signal of one bit, i.e. a serial data stream with one bit amplitude resolution. Each of the stages of the shift register switches a dedicated current source ON or OFF. The currents thus generated by all of the stages of the shift register are added to generate an output current of the FIRDAC. Usually, the output current is applied to a current-to-voltage converter to generate an analog output voltage of the FIRDAC. Each stage of the FIRDAC produces an output current contributing to the overall output current of the FIRDAC. However, the stages of the FIRDAC do not all contribute in the same extent. In order to obtain a desired filter characteristic, each stage of the FIRDAC has an associated weighting coefficient, which is constituted by the magnitude of the output current of the current source.
In a typical application situation, the FIRDAC is used in a signal-processing path of a mobile telephone for providing an analog audio signal to a speaker or earphone. The FIRDAC receives its input bitstream signal from a noise shaper, which increases the signal-to-noise ratio of the FIRDAC by shifting quantisation noise from the voice band to higher frequencies. Due to spurious influences, noise shapers have a tendency of repeating certain patterns, leading to small audible tones, called “idle tones”. In order to prevent said idle tones from being audible, it is known per se to digitally offset the noise shaper with a fixed amount, called “DC dither”, resulting in the idle tones being pushed to a high frequency above an audible level.
A problem in this respect is that the fixed offset of the noise shaper causes an offset in the FIRDAC, and hence an offset in a driver which receives the FIRDAC output signal and generates a driving signal for the earphone or speaker. In practical cases, the offset can be as much as 80 mV. With earphones having a resistance of 8-16 Ohm, this leads to a large and undesirable current consumption in the order of 10 mA.
The present invention aims to overcome this problem.
More particularly, the present invention aims to overcome said problem without having to increase any chip area occupied by the FIRDAC.
According to an important aspect of the present invention, a current output terminal of the FIRDAC is coupled to a constant current source or sink, adding or subtracting a constant compensation current to or from the output current of the FIRDAC in order to compensate or, preferably, to eliminate said offset.
According to a further aspect of the present invention, in a preferred embodiment, each stage of the FIRDAC comprises in combination a D-flipflop, a PMOS current mirror, and an NMOS current mirror. Each stage of the FIRDAC occupies substantially the same semiconductor space. The flipflops all have the same width, but the transistor widths of the PMOS current mirrors and the transistor widths of the NMOS current mirrors are different and determine the magnitude of the current output of said mirror in order to implement the weighting coefficient of each stage. Consequently, in FIRDAC stages with a relatively low weighting coefficient, the size of the PMOS current mirror and the size of the NMOS current mirror is relatively small, hence a relatively large amount of space is “free”. In said free space, dummy current sources are arranged.
As a consequence of the DC offset in the bitstream generator (“noise-shaper”) , the FIRDAC itself has an offset output level. More particularly, a positive current output of the FIRDAC produces too much positive current whereas a negative current output produces too much negative current. According to an important aspect of the present invention, this is compensated by a constant current source being coupled to a current output.
In the case of a positive current output which produces too much positive current, the invention provides a predetermined number of spare dummy NMOS current sinks that are continuously ON, and which sink away the excess current (the offset) from the positive current sources to ground.
In the case of a negative current output which produces too much negative current, the invention provides a predetermined number of spare dummy PMOS current sources that are continuously ON, and which supplement the excess current (the offset) drawn to ground by the negative current sources.
The amount of offset in the bitstream generator generating the bitstream as input signal for the FIRDAC is known and constant. This means that, before manufacture of the FIRDAC, it is possible to calculate how much compensating current is to be conducted by the dummy NMOS current sources. Hence, it is possible to predetermine which dummies to use and which not.
If the available number of NMOS dummies appears to be too small for an adequate compensation, it is possible to use PMOS dummies for compensation.
REFERENCES:
patent: 5508702 (1996-04-01), Estrada et al.
patent: 6100833 (2000-08-01), Park
patent: 6177896 (2001-01-01), Min
patent: 6229466 (2001-05-01), Gattani
patent: 6232903 (2001-05-01), Koifman et al.
patent: 6424278 (2002-07-01), Groeneweg
Lauture Joseph
Tokar Michael
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