Finite field multiplier with intrinsic modular reduction

Details Finite field multiplier with intrinsic modular reduction Finite field multiplier with intrinsic modular reduction

1997-12-24

2001-05-08

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06230179

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and apparatus for performing finite field and integer arithmetic.
BACKGROUND OF THE INVENTION
Elliptic Curve(EC) cryptography over a finite field require arithmetic operations of addition, multiplication, squaring and inversion. Additionally, subtraction operations are also required if the field is not of characteristic two. Modular arithmetic operations are also required, for example in computing signatures, however these operations are required less frequently than the finite field operations. EC cryptography as an example, requires the full complement of modular operations, addition, subtraction, multiplication and inversion.
Field sizes for cryptography tend to be relatively large, requiring fast, dedicated processors to perform the arithmetic operations in an acceptable time. Thus there have been numerous implementations of either fast modular arithmetic processor or dedicated processors for performing arithmetic operations in F
2
m
.
Traditionally RSA was the encryption system of choice, however with the advent of superior and more secure EC cryptography the need for processors that perform modular exponentiation exclusively is becoming less imperative. Thus while users are in transition from RSA cryptography to EC cryptography there is a need for an arithmetic processor that supports both these operations, with little or no penalty in performance.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a processor that combines finite field arithmetic and integer arithmetic and for providing operations required for EC cryptography.
It is a further object of the invention to provide an arithmetic processor design that may be scaled to different field or register sizes.
A still further object of the invention to provide an arithmetic processor that may be used with different field sizes.
A still further object of the invention is to provide an arithmetic processor that is capable of being scaled to provide an increase in speed when performing multi-sequence operations by simultaneously executing multiple steps in the sequence.
In accordance with an embodiment of the invention there is provided an arithmetic processor that performs both finite field arithmetic and integer arithmetic and in which both special purpose registers and general purpose registers, and arithmetic circuits, are shared. For this purpose, a polynomial basis for the finite field hardware will be assumed, since this basis is similar to the standard radix-power basis of the integers.
In accordance with a further embodiment of the invention, there is provided a processor that includes finite field circuitry and integer arithmetic circuitry and which includes general-purpose registers, and special-purpose registers, wherein the special-purpose registers are not shared by the arithmetic circuitry.
In accordance with this invention there is provide an arithmetic processor comprising: finite field arithmetic circuitry; integer arithmetic circuitry; and mode control means for selectively enabling either the finite field circuitry or integer arithmetic circuitry.


REFERENCES:
patent: 4216531 (1980-08-01), Chiu
patent: 5467297 (1995-11-01), Zook
patent: 5612910 (1997-03-01), Meyer
patent: 5854759 (1998-12-01), Kaliski, Jr. et al.
patent: 5999959 (1999-12-01), Weng et al.
patent: 6049815 (2000-04-01), Lambert et al.

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