Finite field multiplier

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G06F 752

Patent

active

042165318

ABSTRACT:
A multiplier for use with polynomials in an error correction system wherein the multiplier and multiplicand are first encoded from m bits to N bits, where N is greater than m, and wherein the multiplication is accomplished on a bit basis by arrays of AND gates and where the resultant product is decoded from R bits to S bits where S is less than R.

REFERENCES:
patent: 4037093 (1977-07-01), Gregg et al.

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