Fine-tuning phase-locked loop PLL using variable resistor...

Details Fine-tuning phase-locked loop PLL using variable resistor... Fine-tuning phase-locked loop PLL using variable resistor...

2000-10-05

2001-08-28

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C375S376000

Reexamination Certificate

active

06281727

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to Phase-locked loops (PLL's), and more particularly to finely-tuned dual PLL's.
BACKGROUND OF THE INVENTION
Digital systems often rely on accurate clocks to synchronize the timing of operations and data transfers. A crystal oscillator is often used to generate a clock at a base frequency, which is then divided or multiplied to create one or more clocks with desired frequencies. External clock can be received and likewise divided or multiplied to produce internal clocks.
Clocks are typically generated from oscillator outputs using phase-locked loops (PLL's). PLLs are one of the most widely use building blocks in digital systems today. See for example, U.S. Pat. No. 6,124,741 by Arcus, and assigned to Pericom Semiconductor Corp. of San Jose, Calif.
FIG. 1
illustrates a typical PLL. Phase detector
10
receives a reference-clock input from an external oscillator or clock source. The phase and frequency of the reference clock is compared to the phase and frequency of a feedback clock generated by voltage-controlled oscillator (VCO)
14
. The feedback clock can be the output clock generated by the PLL, or a divided-down derivative of the output clock from VCO
14
. Phase detector
10
outputs up and down signals UP, DN when the phase or frequency of one input does not match the phase or frequency of the other input. These up and down signals cause charge pump
12
to add or remove charge from filter capacitor
19
, which integrates the charge. As charge is added or removed from filter capacitor
19
, the voltage input to VCO
14
is increased or decreased. VCO
14
responds by increasing or decreasing the frequency of the output clock. The feedback clock to phase detector
10
is likewise changed by VCO
14
.
As charge pump
12
adds or removes charge from filter capacitor
19
, altering control voltage V
CTL
input to VCO
14
, the phase and frequency of the feedback clock are adjusted until the reference clock is matched. Then phase detector
10
stops generating up and down signals to charge pump
12
, until charge leaks off filter capacitor
19
or the reference clock changes.
Often the reference or input frequency is not exactly the same as the desired output frequency. The reference frequency may be divided or multiplied to obtain the output frequency, but the desired output frequency may still not be a multiple or divisor of the reference frequency. For example, the desired frequency may be an abstract frequency completely unrelated to the reference frequency. In the past, the system designer chose the reference frequency to be an exact multiple or divisor of the desired frequency.
Various PLL's with multiple loops have been developed. See U.S. Pat. Nos. 5,943,382 by Li et al., 5,393,250 by Imaizumi et al., 5,075,639 by Taya, and 5,317,284 by Yang. While useful, a dual-loop PLL that outputs a clock with a finely-adjustable frequency is desired.
In some applications, it is desired to finely-tune the output frequency. It is useful to finely tune the output frequency without requiring any change to the reference frequency. Adjustment of the output frequency is desirable. A PLL that uses a fixed reference frequency input, but that can generate a range of finely-tuned output frequencies, is desirable.


REFERENCES:
patent: 4929918 (1990-05-01), Chung et al.
patent: 5075639 (1991-12-01), Taya
patent: 5317284 (1994-05-01), Yang
patent: 5329250 (1994-07-01), Imaizumi et al.
patent: 5414390 (1995-05-01), Kovacs et al.
patent: 5418497 (1995-05-01), Martin
patent: 5422604 (1995-06-01), Jokura
patent: 5534822 (1996-07-01), Taniguchi et al.
patent: 5570395 (1996-10-01), Myers
patent: 5610558 (1997-03-01), Mittel et al.
patent: 5646562 (1997-07-01), Abe
patent: 5748044 (1998-05-01), Xue
patent: 5943382 (1999-08-01), Li et al.
patent: 5950115 (1999-09-01), Momtaz et al.
patent: 5977806 (1999-11-01), Kikuchi
patent: 6118316 (2000-09-01), Tamamura et al.
patent: 6188258 (2001-02-01), Nakatani

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