Fine tuning a sampling clock of analog signals having...

Details Fine tuning a sampling clock of analog signals having... Fine tuning a sampling clock of analog signals having...

2008-06-24

2008-06-24

Hjerpe, Richard (Department: 2629)

Computer graphics processing and selective visual display system

Display driving control circuitry

Display power source

C345S211000, C345S212000, C345S099000, C345S204000, C345S690000, C348S510000, C348S512000, C348S513000, C348S536000, C348S537000

Reexamination Certificate

active

07391416

ABSTRACT:
Method and system for fine tuning frequency and phase of a sampling clock of analog signals (R, G, B) having digital information, for sampling the analog signals within an optimal sampling period, enabling optimal display by a digital display device (92). Small amount of information from input signals is required for rapidly and accurately determining values of frequency and phase of the sampling clock. After measuring using a measurement system (96) and obtaining pixel values while sweeping phase values of signals using a phase locked loop (PLL) mechanism (48), there is determining values of two parameters, (i) error of an initial frequency value of the sampling clock (Rx clock), proportional to error of an initial phase locked loop (PLL) division factor value, and (ii) phase of the sampling clock, without need for making additional measurements based on these values, using a control unit (94).

REFERENCES:
patent: 6097437 (2000-08-01), Hwang
patent: 6097444 (2000-08-01), Nakano
patent: 6285344 (2001-09-01), Everard et al.
patent: 6404422 (2002-06-01), Choi
patent: 6833875 (2004-12-01), Yang et al.
patent: PCT WO 03/060623 (2003-07-01), None

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