Fine line circuitization

Details Fine line circuitization Fine line circuitization

2002-09-23

2004-11-23

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C438S597000, C148S033200

Reexamination Certificate

active

06822332

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a circuitized substrate, and more particularly to a substrate having tightly spaced fine line circuitization positioned thereon, and method of forming same.
BACKGROUND OF THE INVENTION
Circuitized substrates, such as chip scale packages, ball grid array substrates, test carriers, multi chip modules, and printed wiring boards, often include patterns of conductors. In addition, conductive vias can be formed to electrically connect the conductors to contacts, or other patterns of conductors, located on different surfaces or internal conductive planes of the circuitized substrate.
The two approaches in the art used in mass production for forming conductors and associated connections to contacts or vias are additive circuitization using pattern plating, and subtractive circuitization following full panel plating. Typically both approaches start with a multilayer composite board or substrate that has been laminated with an external metal foil commoning layer, and which has been drilled with blind vias or through holes to make subsequent connections to internal wiring. The external metal foil, usually copper, may be thinned by chemical or mechanical means to facilitate further processing. In the typical additive circuitization process the conductor pattern is then defined by patterning a photoresist, and formed by electroplating metal into the defined pattern and drilled vias not covered by the resist. After plating, the photoresist is stripped and the original thin metal commoning layer is etched away leaving a pattern of conductors and plated vias/through holes. In the typical subtractive process, the first step after the multilayer composite board has been laminated with an external metal foil commoning layer and drilled is to blanket plate all surfaces, including drilled vias, to a final conductor thickness. The conductor pattern is then formed by patterning a photoresist on metal features to remain. All unwanted metal is removed by a chemical etching leaving a pattern of conductors and plated vias/through holes.
The additive approach to circuitization is generally capable of producing well shaped conductors with fine spacing, since the conductors are built up into channels predefined by resist. The shape and density of the conductors is limited by the ability to define channels in photoresist. However, additive methods have many challenges including uniformity of plating across the panel and inside the plated through holes, adhesion of the resist through processing steps, and problems associated with removing the thin metal commoning layer after the resist is stripped. These challenges only increase as boards become thicker and more complex. Furthermore, additive circuitization processes that use electroless plating to avoid the need for a commoning layer are very expensive, and the electroless plating baths tend to have unstable characteristics requiring close monitoring. The subtractive circuitization approach is inherently more simple, with less process steps, and is less costly. Since there is no commoning layer to remove after the conductors are formed as with additive circuitization, all problems associated with the commoning layer etch process step are avoided. In addition, very uniform plating thickness is obtained across the panel and inside plated through holes independent of board thickness. A main disadvantage of the typical subtractive process is that it is more difficult to produce substantially rectangularly shaped surface conductors of dense spacing since the process is limited by the ability to etch away surface metal, which will not normally result in the same sharp edge definition that is possible by a photopattern in resist. This disadvantage becomes more pronounced as boards become thicker and features become more dense because the process parameters required to plate inside the high aspect ratio drilled vias of thick boards will result in thicker surface plating, which in turn further limits the ability to produce dense and rectangular shaped conductors.
As circuitized substrates become denser, thicker and more complex, it is increasingly more difficult, and in many cases impossible, to use conventional processes to form the conductors. In particular, the required size, spacing and shape of the conductors most often cannot be achieved by using conventional processes, especially solely with a subtractive circuitization process.
FIG. 1
shows a much-enlarged sectional view, in elevation of a known circuitized substrate
10
. The circuitized substrate
10
includes a substrate
12
having a substantially planar upper surface
14
and a plurality of conductors
16
positioned on the substantially planar upper surface of the substrate. A photoimageable photopatterned dielectric material
18
is positioned on an upper surface
20
of plurality of conductors
16
.
Plurality of conductors
16
are formed using solely the conventional subtractive circuitization process described above. A conductive layer is blanket deposited on substrate
12
, photopatterned with photoimageable dielectric material to expose portions of the conductive layer and then chemically etched to form plurality of conductors
16
. The conductive layer includes a side wall
24
therein defining an opening
26
. Chemical etching action, being substantially uniform on the exposed portions of the conductive layer, shapes side wall
24
in a curved concave manner and can form undercut regions
28
, especially when the thickness of the conductive layer is greater than about 8 microns. The resultant shape in cross-section of conductors
16
is that of a half hourglass. In general, this half hourglass shape has poorer electrical performance characteristics and lower current carrying capability than substantially rectangular cross-sectional shaped conductors of the same height, width, and spacing. Furthermore, the half hourglass shape clearly limits the conductor density (number of conductors per unit area) because conductors of such shape cannot be placed as closely together as rectangular shaped conductors without creating yield (potential shorting), reliability, and electrical concerns. Conductors
16
can be acceptable when electrical performance is not important, that is, when tight spacing between the center to center dimension of the conductors is not a requirement, and when there is no need for features, such as vias, to be located between conductors. When one or all of these factors is desired, half hourglass shaped conductors are undesirable. Tight spacing between the center to center dimension of plurality of conductors
16
is difficult to achieve by chemical etching without the bases
30
of the plurality of conductors touching one another or being substantially close to touching one another creating a potential short or cross-talk between adjacent conductors.
In the industry today, these problems can be addressed by specifying the conductive layer and the resultant conductors to have a thickness of less than about 8 microns. The undercutting action of chemical etching on a conductor layer having a thickness of less than about 8 microns is of short duration with less pronounced undercutting. However, conductors having a thickness of less than about 8 microns still can have poor electrical characteristics and do have lower current carrying capability. Moreover, about 8 microns of surface copper is not a realistic limit with thick boards that include high aspect through holes that need complete plating throughout, as discussed above. When the thickness of conductors greater than about 8 microns is required in combination with tightly spaced fine lines, sufficiently more etching is required to increase the spacing between the base of the conductors. More etching increases undercutting of the conductors, makes the half hourglass shape more pronounced, and thins the distance between sidewalls of an individual conductor even further resulting in conductors having even poorer electrical performance.
FIG. 2
illustrates circuitized substr

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