Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
1999-10-13
2002-03-26
Maung, Zarni (Department: 2154)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C712S209000, C711S202000, C711S206000, C703S027000
Reexamination Certificate
active
06363336
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for detecting attempts by a microprocessor which dynamically translates instructions from a target to a host instruction set to write to memory storing target instructions which have already been translated.
2. History of the Prior Art
Recently, a new microprocessor was developed which combines a simple but very fast host processor (called a “morph host”) and software (referred to as “code morphing software”) to execute application programs designed for a processor having an instruction set different than the instruction set of the morph host processor. The morph host processor executes the code morphing software which translates the application programs dynamically into host processor instructions which are able to accomplish the purpose of the original software. As the instructions are translated, they are stored in a translation buffer where they may be executed without further translation. Although the initial translation of a program is slow, once translated, many of the steps normally required for hardware to execute a program are eliminated. The new microprocessor has proven able to execute translated “target” programs as fast as the “target” processor for which the programs were designed.
The morph host processor includes a number of hardware enhancements which allow sequences of target instructions spanning known states of the target processor to be translated into host instructions, stored for further use in the translation buffer, and tested to determine if the translated instructions will execute correctly. These hardware enhancements allow the buffering of the effects of execution of translations until execution has succeeded. Memory stores and target processor state are updated upon successful execution in a process referred as “committing.” These hardware enhancements allow the rapid and accurate handling of exceptions which occur during the execution of the sequences of host instructions by returning execution to the beginning of a sequence of instructions at which known state of the target processor exists. Returning the operations to a point in execution at which target state is known is called “rollback.” The new microprocessor is described in detail in U.S. Pat. No. 5,832,205, Memory Controller For A Microprocessor For Detecting A Failure Of Speculation On The Physical Nature Of A Component Being Addressed, Kelly et al, Nov. 3, 1998, assigned to the assignee of the present invention.
One problem which can arise with the new processor is that it is possible with some operating systems and applications for a target processor to write to target instructions stored in memory. If this happens, the host instructions which are translations of the target instructions which have been overwritten are no longer valid. In order to assure that invalid host translations are not used, the new processor utilizes an indicator termed a “T bit.” The T bit is stored with a physical page address in a translation lookaside buffer (TLB). A lookaside buffer stores entries including both the virtual and physical memory addresses of recent memory accesses allowing memory to be more rapidly accessed than through page tables. Each entry in the TLB of the new processor includes a T bit which is set whenever instructions on the addressed memory page have been translated to host instructions. If a write is attempted to a memory page protected by a T bit, a T bit exception is generated. A T bit exception causes an exception handler to look up a data structure which holds references to addresses of host instructions translated from the target instructions on the page protected by the T bit. The exception handler invalidates these translations by turning off the T bit protection for the TLB entry.
The arrangement for utilizing T bits is described in detail in U.S. patent application Ser. No. 08/702,771, entitled Translated Memory Protection Apparatus For An Advanced Microprocessor, Kelly et al, filed Aug. 22, 1996, and assigned to the assignee of the present invention.
Although the arrangement which utilizes T bits in TLB entries functions efficiently in most situations, some problems in operation remain. One of these problems is that certain target processors employ operating systems which do not discriminate between areas in which instructions and data are stored. For example, Microsoft Windows allows segments designated for instructions and other segments designated for data to be stored on the same memory pages.
If this occurs, an attempt to write to the data on such a memory page generates a T bit fault. The resulting exception causes all translations of target instructions on the memory page protected by the particular T bit to be invalidated even though a write to data does not indicate that any target instruction has changed. The invalidation of the correct translations on the memory page significantly slows the operation of the new microprocessor.
It is desirable to improve the operational speed of the new microprocessor by eliminating the invalidation of translations which are not affected by writes to memory pages protected by T bits and reducing the number of T bit traps taken that do not cause invalidation of translations.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a faster microprocessor compatible with and capable of running application programs and operating systems designed for other microprocessors at a faster rate than those other microprocessors.
This and other objects of the present invention are realized in a computer which translates instructions from a target instruction set to a host instruction set by a method for determining if writes to a memory page are directed to target instructions which have been translated to host instructions in a computer which translates instructions from a target instruction set to a host instruction set, including the steps of detecting a write to a memory page storing target instructions which have been translated to host instructions, detecting whether a sub-area of the memory page to which the write is addressed stores target instructions which have been translated, and invalidating host instructions translated from addressed target instructions.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.
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Anvin H. Peter
Banning John
Gribstad Benjamin
Keppel David
Klaiber Alex
King Stephen L.
Lin Wen-Tai
Maung Zarni
Transmeta Corporation
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