Final passivation scheme for integrated circuits

Details Final passivation scheme for integrated circuits Final passivation scheme for integrated circuits

2007-12-11

2007-12-11

Zarneke, David A. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257SE23173

Reexamination Certificate

active

10847901

ABSTRACT:
A semiconductor device includes a substrate with an active area. A last level interconnect capping layer is disposed over the active area. A buffer layer/crack stop layer overlies the last level interconnect capping layer and a passivation layer overlies the buffer layer/crack stop layer. Also, a contact pad (e.g., probe pad, wire bond pad or flip-chip pad) overlies the passivation layer.

REFERENCES:
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patent: 6713873 (2004-03-01), O'Loughlin et al.
patent: 6774059 (2004-08-01), Chuang et al.
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patent: 6849536 (2005-02-01), Lee et al.
patent: 6949830 (2005-09-01), Owada et al.
patent: 7005752 (2006-02-01), Bojkov et al.
patent: 2002/0014705 (2002-02-01), Ishio et al.

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