Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2002-01-28
2004-04-13
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S385000, C438S238000, C438S381000, C257S722000
Reexamination Certificate
active
06720231
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to semiconductor device manufacturing, and more particularly to a method of forming a resistor within a thin vertically oriented semiconductor body (Fin) as well as the semiconductor structure this is formed by the inventive method. The present invention also provides a method of controlling the resistance of a plurality of vertically oriented semiconductor bodies as well as a method to eliminate the nominal variation on the Fin thickness from the variation on threshold voltage.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects. As is known to those skilled in the art, short-channel effects are the decrease of threshold voltage Vt in short-channel devices due to two-dimensional electrostatic charge sharing between the gate and the source/drain diffusion regions.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness has to be reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 Â&mgr;m MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of a typical prior art double-gated MOSFET consists of a very thin vertical Si layer (Fin) for the channel, with two gates, one on each side of the channel. The term “Fin” is used herein to denote a semiconducting material which is employed as the body of the FET. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
Resistors are devices that have electrical resistance associated therewith. Resistors are typically employed in an electrical device for protection, operation and/or current control. Hence, resistors play an important part in current analog and digital circuit designs. To date, however, there are no known Fin structures that include a resistor built within the Fin of the structure. Using a Fin-based technology would require a redesign of current CMOS (complementary metal oxide semiconductor) resistor schemes for buried resistors (BRs), overpass resistors (Ops) and silicide resistors.
In view of the above, there is a need for providing Fin structures which include a resistor built within the thin vertical semiconductor body of the structure that do not require redesign of current CMOS resistor schemes.
BRIEF SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a Fin structure having a resistor formed within a thin vertically oriented semiconductor body of the Fin structure.
A further object of the present invention is to provide a method of fabricating a Fin structure having a resistor formed within a thin vertically oriented semiconductor body of the Fin structure that can be easily implemented with various CMOS resistor design layouts such as buried resistors, overpass resistors and silicide resistors.
An even further object of the present invention is to provide a method of controlling the resistance of a plurality of vertically oriented semiconductor bodies.
A yet even further object of the present invention is to provide a method which is capable of eliminating the nominal variation on the Fin thickness from the variation on threshold voltage.
These and other objects and advantages are achieved in the present invention by utilizing an off-axis implant step to implant dopant ions into exposed vertical surfaces of a thin vertically oriented semiconductor body of a Fin structure such that the concentration and energy employed during the implant step is sufficient enough to penetrate into the surface of the vertically oriented semiconductor body without saturating the semiconductor body.
Specifically, and in one aspect, the present invention relates to a method of forming a resistor within a Fin structure. Specifically, the method of forming the resistor in such a structure includes the steps of:
forming at least one vertically oriented semiconductor body having exposed vertical surfaces on a substrate;
implanting dopant ions into said exposed vertical surfaces of said at least one semiconductor body off-axis at a concentration and energy sufficient to penetrate into said exposed vertical surfaces of said at least one semiconductor body without saturation; and
forming contacts to said at least one semiconductor body.
The above processing steps result in the formation of a Fin structure which includes a resistor present within the at least one vertically oriented semiconductor body. Specifically, the inventive Fin structure comprises:
a structure having at least one vertically oriented semiconductor body present thereon, wherein said at least one vertically oriented semiconductor body has vertical surfaces;
a doped region present in said at least one vertically oriented semiconductor body that extends inward from said vertical surfaces; and
contacts present on outer portions of said at least one vertically oriented semiconductor body.
In some embodiments of the present invention, the structure includes a masking layer which protects predetermined portions of said at least one vertically oriented semiconductor body, while leaving said contacts exposed. It is noted that the resistor element of the present invention includes the doped region as well as the contacts which are formed within the semiconductor body of the structure.
Another aspect of the present invention relates to a method of controlling the resistance of a plurality of vertically oriented semiconductor bodies, each having exposed surfaces and different widths. Specifically, this aspect of the present invention comprises the steps of:
forming a structure having a plurality of vertically oriented semiconductor bodies on a substrate, each of said bodies having exposed vertical surfaces and differing widths; and
implanting dopant ions off-axis into said plurality of vertically oriented semiconductor bodies at a concentration and energy sufficient to penetrate into exposed vertical surfaces of said plurality of vertically oriented semiconductor bodies without saturating each semiconductor body.
In some embodiments, an activation-annealing step follows the implant step so as to diffuse the dopant ions from the vertical surfaces of each semiconductor body. In such cases, the thicker semiconductor bodies have a first dopant concentration and thinner semiconductor bodies have a second dopant concentration, wherein the first dopant concentration is lower than said second dopant concentration.
REFERENCES:
patent: 3798753 (1974-03-01), Camenzind et al.
patent: 4065742 (1977-12-01), Kendall et al.
patent: 4191964 (1980-03-01), Kant
patent: 4296428 (1981-10-01), Haraszti
patent: 4416049 (1983-11-01), McElroy
patent: 4743565 (1988-05-01), Goth et al.
patent: 4825081 (1989-04-01), Wille et al.
patent: 4893166 (1990-01-01), Geekie
patent: 5102812 (1992-04-01), Caneau et al.
patent: 5172211 (1992-12-01), Godinho et al.
patent:
Fried David M.
Nowak Edward J.
Luu Chuong A
Sabo William D.
Smith Matthew
LandOfFree
Fin-type resistors does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fin-type resistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fin-type resistors will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3189440