Filtering circuit for image signal processing

Details Filtering circuit for image signal processing Filtering circuit for image signal processing

2000-03-24

2004-02-24

Boudreau, Leo (Department: 2724)

Image analysis

Image enhancement or restoration

Image filter

C382S265000

Reexamination Certificate

active

06697533

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a filtering circuit and, more particularly, to a filtering circuit with simplified structure for image signal processing.
2. Description of Related Art
Generally, in the image signal compression process which employs, for example, a wavelet filter to process image signals, as shown in
FIG. 3
, image signals must be stored first, and then applied to a high frequency filter
31
and a low frequency filter
32
to perform filtering and down sampling processes. Therefore, an input image signal line
33
with 2N length is converted into N high frequency signal points and N low frequency signal points. These high and low frequency signals are then respectively encoded and compressed.
It is known that a digital filter is provided to perform an operation expressed by the following equation:
y
n
=
∑
i
=
0
N
-
1
⁢
 
⁢
c
i
⁢
x
n
-
i
,
where N is the order of a filter, x
n
is the n-th input, y
n
is the n-th output, and c
i
(i=0 . . . N−1) is the constant coefficient of the filter. The coefficient of the above high frequency filter
31
is (0, 1, −2, 1, 0), and the coefficient of the low frequency filter
32
is (−1, 2, 6, 2, −1). Therefore, the high frequency filter
31
can be described by an equation as follows:
H
2n
=X
2n
−2
X
2n−1
+X
2n−2
.
The equation that describes the low frequency filter
32
is:
 
L
2n
=−X
2n
+2
X
2n−1
+6
X
2n−2
+2
X
2n−3
−X
2n−4
.
Based on the above equations, a typical architecture for processing the high and low frequency signals of a 3-5 (3 stages and 5 levels) wavelet filter is shown in FIG.
4
. As shown, in a first stage, an input image signal is first filtered to produce a high frequency component y
1
d
and a low frequency component y
1
a
. Next, in a second stage, the low frequency component y
1
a
is further filtered to produce a high frequency component y
2
d
and a low frequency component y
2
a
. Then, in a third stage, the low frequency component y
2
a
is further filtered to produce a high frequency component y
3
d
and a low frequency component y
3
a
. In such a filtering process, the high and low frequency signals are processed separately such that different hardware architectures are required to process the high and low frequency signals. Practically, in each individual stage, five registers
41
are required to hold and delay the image signals, and eight shift adders
42
are required to multiply filtering coefficients and input values for performing filtering operations. Thus, a total of 5×3=15 registers and 8×3=24 adders are required. In view of the foregoing, such a conventional filtering architecture employs too many registers and adders, and thus the circuit design is complicated and the manufacturing cost is high.
U.S. Pat. No. 5,838,377 entitled “Video Compressed Circuit Using Recursive Wavelet Filtering” discloses a filtering architecture in which the number of adders is reduced. Under the same processing condition as the above example, there are only 5×3=15 adders required. However, the number of registers required to perform the filtering operation is not reduced so that the simplification in hardware architecture is not satisfactory. Therefore, there is a need to have a novel filtering circuit to mitigate and/or obviate the aforementioned problems.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a filtering circuit for image signal processing which utilizes the high frequency component to obtain the high frequency component, and employing a small amount of adders to perform the filtering operation, thereby effectively simplifying the circuit structure.
To achieve the above object, a filtering circuit is provided for performing a high pass filtering and a low pass filtering on a plurality of input image data to obtain a high frequency component and a low frequency component corresponding to a current input image data. In the filtering circuit, a first latch is provided for holding the input image data and outputting the same. A first adder is provided for performing an addition of a previous input image data and a previous second input image data in a first operating cycle to obtain a first operation value, and performing an addition of the first operation value and a current input image data in a second operating cycle to obtain a corresponding high frequency component. A second latch is provided for holding the first operation value and the high frequency component from the first adder and outputting the same. A second adder is provided for performing an addition of a previous second high frequency component output from the second latch and the previous second input image data in the first operating cycle to obtain a second operation value, and performing an addition of the second operation value and a current high frequency component obtained in the first adder in the second operating cycle to obtain a corresponding low frequency component. A third latch is provided for holding the second operation value and outputting the same.


REFERENCES:
patent: 5260888 (1993-11-01), Sharman
patent: 5838377 (1998-11-01), Greene
patent: 5984514 (1999-11-01), Greene et al.
patent: 6314132 (2001-11-01), Liu et al.

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