Filter with multipliers operating in ones complement arithmetic

Details Filter with multipliers operating in ones complement arithmetic Filter with multipliers operating in ones complement arithmetic

2007-01-23

2007-01-23

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S323000

Reexamination Certificate

active

10320767

ABSTRACT:
A finite impulse response filter, including a plurality of taps arranged to receive and process a sequence of input data samples so as to generate a filter output. Each tap consists of a multiplier operating in one's complement arithmetic, the multiplier being coupled to multiply a respective input sample from the sequence by a respective equalization coefficient, and an adder, which sums an output from the multiplier. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The filter also includes an adjustment-accumulator coupled to receive the filter output and responsive thereto to generate an adjustment that is adapted to correct the filter output to a twos complement result, and an adjustment-adder which sums the adjustment and the filter output to generate a final output.

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