Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
1997-09-26
2002-04-23
Chin, Stephen (Department: 2634)
Pulse or digital communications
Equalizers
Automatic
C708S322000
Reexamination Certificate
active
06377619
ABSTRACT:
TECHNICAL FIELD
This invention relates to finite impulse response (FIR) filters, and more particularly, to FIR filters using time multiplexed multipliers with multiple coefficients per multiplier.
BACKGROUND OF THE INVENTION
Prior art finite impulse response (FIR) filters employ fixed delay lines for the input samples. Such delay lines are implemented using a series of edge triggered flip flops. As a result, in operation, the prior art delay lines consume more power than is desirable. In addition, prior art FIR filters are typically developed using a single filter structure, and thus lack the flexibility to implement different types of filters.
SUMMARY OF THE INVENTION
In accordance with the principles of the invention, the fixed delay line of prior art finite impulse response (FIR) filters is eliminated. Instead, multiported register files are employed to implement the input delays necessary for filter operation.
A multiported register file is a memory, typically small, e.g., having a capacity for four words, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register file may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port.
In accordance with an aspect of the invention, an FIR filter arranged to employ multiported register files to store sample data has at least one output of each multiported register file coupled to the input of the next stage of the FIR filter, if any. In addition, each multiported register file feeds data from one output to the multiply-add portion of its associated stage of the FIR filter. Note that these outputs may be the same.
When the introduction of at least one sample delay for a particular sample is necessary, the multiported register file storing that sample is operated to supply, as an output, data that was previously stored therein, regardless of any data currently being supplied to it as input. In contrast, when no sample delay is required for a particular sample to reach a particular multiported register file, the multiported register files in the path of that sample are operated in a lookthrough mode. The lookthrough mode is a mode in which a sample supplied to a multiported register file's input port is passed directly to at least one of its output ports. Doing so enables a regular structure to be maintained.
In one embodiment of the invention, instead of separately supplying read and write addresses for each multiported register file, the addresses are supplied in a pipelined manner, so that only one read and write address generator is necessary for the entire filter. The write enable signal may also be pipelined, depending on the function implemented by the FIR filter.
Multiported register files may also be used to store coefficients for the FIR filter, especially if the filter is an adaptive one, and so its coefficients are changing.
Advantageously, low power is achieved over the prior art FIR filters. In addition, flexibility is afforded to the filter designer to implement with a single filter implementation many different filter structures.
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John L. Hennessy and David A. Patterson, “Computer Organization and Design”-2nded.; pp. 345-346 amd B-25-B (1997).
Denk Tracy C.
Larsson Patrik
Nicol Christopher John
Agere Systems Guardian Corp.
Chin Stephen
Fan Chieh M.
Gamburd Nancy R.
Rosenthal Eugene J.
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