Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2000-03-27
2003-03-11
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S319000
Reexamination Certificate
active
06532483
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the field of communications. The present invention relates to an apparatus and a method for filtering a plurality of data trains by time division multiplexing.
There are many applications in which two or more digital data streams or trains have to be filtered in the same way. In television technology, for instance, it may be necessary for data triplets, such as trains of RGB or YUV data to be decimated by the same factor.
In multiplex transmission of a plurality of data trains over a common channel, it can also become necessary to adapt the bandwidth of the data trains to the transmission bandwidth of the channel by low-pass filtering that is uniform for all the trains. The maximum frequency present in each data train must not be any higher than ½n times the scanning frequency or the transmission frequency of the channel. Otherwise, problems known as aliases occur.
To keep these problems as slight as possible, it is typical to low-pass filter the data trains individually before their transmission over the channel. After the filtration, a new train is formed from the plurality of data trains with the aid of a reversing switch; the new train is composed cyclically of values from the different starting trains and can be transmitted over the channel.
The low-pass filters used for such purpose have transfer functions of the following form, for example
H
(
z
−1
)=(1−
z
−1
)
m
and include a series circuit of register-adder units, in which the inputs of the adders are each connected once directly and once through a delay register to the input of the unit.
These conventional filters, because of their construction, determine one output value for each input value of an original train. It is possible that because of a limited transmission capacity of the transmission channel, only some of these values can be picked up; this means that the others were determined in vain.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an apparatus and a method for filtering a plurality of data trains by time division multiplexing that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that make it possible to reduce the expense for circuitry involved in reserving a separate filter for each original data train, and thus to minimize the substrate area required for integrating such filters.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a filter for filtering n data trains by time division multiplexing, in which n is an integer>1, including data channels for receiving values of the n data trains, registers for buffer storage of at least one of the values of the n data trains and derived values derived from the n data trains, the registers subdivided into n groups, each of the n groups of the registers connected to at least one of the data channels for receiving the values of the n data trains, and adders each having a first input and a second input, the adders and the registers alternatively connected to one another to form a chain, the first input of each respective adder connected upstream of a respective one of the registers of an i
th
group (0≦i≦n−1) of the n groups has a connection to a respective one of the data channels assigned to the i
th
group of the n groups, and the second input of a corresponding respective adder connected to a respective one of the registers of a group having a number (i−1)mod n without an intervening register of another of the groups.
The structure of the filter makes it possible to process a plurality of data trains simultaneously in one and the same filter, and, at every instant, the registers of one group contain only values that are derived from the values of a single one of the original trains.
Each time the registers of the filter are activated in order to store the values applied to their input, these values move onward only to the next group, without being affected by the values of other trains.
In accordance with another feature of the invention, there is provided a multiplier disposed between each of the n groups and at least one of the data channels.
In accordance with a further feature of the invention, there are provided parallel multipliers for multiplication by various factors, the parallel multipliers disposed between each of the n groups and at least one of the data channels, and a switch for selectively connecting one of the multipliers with a respective one of the adders.
In accordance with an added feature of the invention, there is provided at least one multiplier for multiplication by a factor k not a power of two, the at least one multiplier disposed between each of the n groups and at least one of the data channels and having parallel submultipliers for multiplying by a power of two (2
j
), the parallel submultipliers having input data lines and output lines, the parallel submultipliers having a connection of the input data lines to the output lines each left-shifted by j bits, and further adders connected to the parallel submultipliers adding output values of the parallel submultipliers.
In accordance with an additional feature of the invention, the chain has m adders of the adders with an output and m registers of the registers with an input, an input of a 0
th
register of the registers is connected to a respective data channel, and an input of a j
th
register is connected to an output of a (j−1)
th
adder for all j>0, the chain realizing a transfer function (H(z
−1
)=&Sgr;a
j
z
−j
) represented as a polynomial in z
−1
where j=0, 1, . . . , m−1.
The filter according to the invention with a polynomial transfer function H(z
−1
)=&Sgr;a
j
z
−j
can be constructed as a series circuit of m register-adder units; the first input of the 0
th
unit is connected to the associated signal channel, and the first inputs of all the other units are each connected to the output of the unit immediately preceding each of them.
In accordance with yet another feature of the invention, there is provided a multiplier, the m adders having an input, and the input of a j
th
adder of the m adders being connected to a respective data channel through the multiplier for multiplication by the factor a
j
for all a
j
≠1.
A filter according to the invention is simple to construct by providing, for all factors a
j
≠1 of the transfer function, one multiplier for multiplication by the factor a
j
, which connects the second input of the j
th
unit to the assigned data channel.
Multipliers for multiplication by a power of two 2
j
can be formed in a very simple way by a submultiplier that contains only a single data line, whose bit inputs are each linked with outputs whose value is higher by j bits.
Multipliers for multiplication by an arbitrary factor can be constructed from a plurality of submultipliers, in accordance with the powers of two contained in the factor, and adders for adding the outputs of the submultipliers.
In accordance with yet a further feature of the invention, at least one of the n groups has two registers of the registers each with an output, and at least one adder of the adders has two inputs respectively connected to the output of the two registers.
In accordance with yet an added feature of the invention, there is provided a switch, the registers each having an output, and the switch connecting an output of a register of a group (i+1)mod n(0≦i≦n−1) of the registers selectively to at least one of the first input and the second input of respective adders connected upstream of respective registers of the registers of a group i of the n groups.
In accordance with yet an additional feature of the invention, there is provided a switch, the registers each having an output, and the switch connecting an input of a respective adder of the adders connected upstream of a register of a group (i+1)mod n(0&
Mehrgardt Sönke
Nie Xiaoning
Wendel Dirk
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Ngo Chuong Dinh
Stemer Werner H.
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