Filter circuit with reduced number of delay elements and adders

Details Filter circuit with reduced number of delay elements and adders Filter circuit with reduced number of delay elements and adders

1997-07-15

1999-03-23

Malzahn, David H.

Boots, shoes, and leggings

364749, G06F 1710

Patent

active

058869140

ABSTRACT:
An output from an adder 10.sub.1, i.e., an output of a first bit plane is inputted to an adder 10.sub.6 through delay elements 2.sub.2 and 3.sub.0 and a multiplier 100.sub.0. On the other hand, input data X are inputted to multipliers C.sub.2.sup.1 to C.sub.0.sup.1 through a delay element 1.sub.0 and multiplied by the respective multipliers to obtain partial products. An adder 10.sub.2 receives a partial product by the multiplier C.sub.2.sup.1 through a delay element 2.sub.3 and a partial product by the multiplier C.sub.1.sup.1. An adder 10.sub.3 receives an output from the adder 10.sub.2 through the delay element 2.sub.3 and on the other hand a partial product by the multiplier C.sub.0.sup.1. An output from the adder 10.sub.3, i.e., an output of a second bit plane is inputted to the adder 10.sub.6 through a delay element 2.sub.5. The adder 10.sub.6 performs addition of the output from the adder 10.sub.3, i.e., the output of the second bit plane and the output from the adder 10.sub.1, i.e., the output of the first bit plane, to output the addition result. This structure allows reduction in the number of delay elements and adders, to achieve a filter circuit downsized in circuit scale.

REFERENCES:
patent: 4941121 (1990-07-01), Zurawski
patent: 5530661 (1996-06-01), Garbe et al.
IEEE International Solid State Circuits Conference, 1987, "A 40 Mhz Programmable Semi Systolic Transversal Filter", Noll et al., pp. 180-181, 390-391.
IEEE Transactions on Circuits and Systems--II:Analog and Digital Processing, vol. 43., No. 10, Oct. 1996, "Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers", Hartley, pp. 677-688.

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