Filter circuit utilizing reversible counter for generating a sat

Details Filter circuit utilizing reversible counter for generating a sat Filter circuit utilizing reversible counter for generating a sat

1989-02-13

1990-10-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307523, 307528, 328165, 328167, H03B 100, H03K 906

Patent

active

049610147

ABSTRACT:
A filter circuit uses a reversible counter to eliminate noise from an input signal which changes between high and low levels. The input signal is sampled in response to a clock signal of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.

REFERENCES:
patent: 4423383 (1983-12-01), Svendsen
patent: 4556842 (1985-12-01), Rosswurm
patent: 4667338 (1987-05-01), Toyonaga et al.
R. C. Mattern, "Incrementing/Decrementing Binary Counter/Register/Decoder", IBM Technical Disclosure Bulletin, vol. 15, No. 5, Oct. 1972, pp. 1716-1719.
A. Jordan, Jr., "Digital Filter", IBM Technical Disclosure Bulletin, vol. 24, No. 9, Feb. 1982, pp. 4860-4861.

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