Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
1998-10-02
2003-05-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S094000, C327S356000, C327S361000, C333S166000
Reexamination Certificate
active
06563373
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a filter circuit applicable to a matched filter for a spread spectrum communication system.
BACKGROUND OF THE INVENTION
A matched filter judges whether two signals are the same. In a spread spectrum communication system, such as mobile cellular radio or wireless local area network (LAN), each user processes a received signal by the matched filter having a spreading code allocated. A correlation peak is detected from the output of the matched filter so that synchronization, acquisition and holding are performed.
When the spreading code is PN(i), chip time is Tc, spreading ratio is M, and an input signal and correlation output are S(t) and R(t) at a time t, the following formula (1) is given.
R
(
t
)
=
∑
i
=
0
M
-
1
PN
(
i
)
·
S
(
t
-
i
·
Tc
)
(
1
)
Here, PN(i) is a sequence of one bit data.
Double sampling or higher order over sampling is necessary for acquisition, so a plurality of matched filters are needed. The calculation of formula (1) is performed in a plurality of matched filters simultaneously, and one of the calculation results is selectively output or a plurality of outputs are added. The matched filter is constructed by a digital circuit or a surface acoustic wave (SAW) device. The former has large circuit size and consumes a lot of electrical power. Therefore it is inadequate for a mobile phone. The latter has a low S/N ratio and it is difficult to incorporate it with other circuits within one large scale integrated circuit (LSI).
The inventors of the present invention have considered the filter circuits above based on an analog calculation circuit. The analog calculation circuit has an inverting amplifier, and input capacitance connected to an input of the amplifier and a feedback capacitance connected between the input and an output of the amplifier. A sampling and holding circuit, adder, multiplication circuit, integration circuit and other circuits of high speed, low power and high accuracy circuits are realized.
FIG.
18
(
a
) shows an example of such an analog calculation circuit. V
1
and V
2
are input terminals, Vo is an output terminal and INV is an inverting amplifier. The inverting amplifier INV consists of CMOS inverters working in an area of transition of output from high level to low level or from low level to high level. An odd number of CMOS inverters, shown as three stages of CMOS inverters
201
,
202
and
203
in the figure, are serially connected. A serial circuit of resistance R and a capacitance C is connected between an input and output of the CMOS inverter
202
. This serial circuit works as a negative feedback circuit as well as a load of the CMOS
202
for decreasing the gain of the inverting amplifier INV. A capacitance Cg is connected to the inverting amplifier INV for phase compensation so that unexpected oscillation is prevented.
Input capacitances C
1
and C
2
are connected between a point B at the input of INV and the input terminal V
1
, and between the point B and V
2
, respectively. A feedback capacitance Cf is connected between the output terminal Vo and the point B.
The gain of the inverting amplifier is very high, so the voltage at the point B is a constant value Vb. The point B is connected to the gate of the transistors of the CMOS inverter
201
and is a floating point or insulated point from any electrical source.
Assuming that the electrical charge of the capacitances is zero at the initial condition, the total charge at point B is zero after voltages V
1
and V
2
are input. Thus resulting in the following formula (2) of “preservation of electrical charge”.
C
1
(V
1
−Vb)=C
2
(V
2
−Vb)+Cf(V
0
−Vb)=0 (2)
When V
1
and V
2
are voltages from the voltage Vb with point B as a reference point, and defining V(1)=V1−Vb, V(2)=+V2−Vb and Vout=Vo−Vb provides formula (3) which is obtained from the formula (2).
Vout
=
-
(
C
1
Cf
V
(
1
)
+
C
2
Cf
V
(
2
)
)
(
3
)
A voltage Vout is output as an inverted voltage of a summation of input voltages V(i) (i=1,2) multiplied by a coefficient (Ci/Cf), a ratio of the input capacitance Ci and the feedback capacitance Cf.
The voltage Vb at the point B is usually Vdd/2 for maximizing the dynamic range. This voltage is called Vref, hereinafter. and Vref=+Vb=Vdd/2.
If C1=C2=Cf, the output voltage Vout=−{V(1)+V(2)}. A summation of both input voltages is thus obtained and, an adder is realized.
As shown in FIG.
18
(
b
), a similar relationship to the above is applicable when more input voltages are input. Then, the formula (4) is obtained.
Vout
=
-
(
C
1
Cf
V
(
1
)
+
C
2
Cf
V
(
2
)
+
…
+
C
i
Cf
V
(
i
)
+
…
+
C
n
Cf
V
(
n
)
)
(
4
)
If the input capacitances Ci (i=1 to n) are equal to Cf, that is, Ci=Cf (i=1 to n), an output voltage is obtained as a summation of input voltages. An adder of a plurality of inputs is realized.
A sampling and holding circuit using the above analog circuit is shown in FIG.
19
. Vin is an input voltage, SW is a sampling switch, Cin is an input capacitance connected to the input of the inverting amplifier INV, Cf is a feedback capacitance and Vout is an output voltage. The input capacitance and the feedback capacitance have equal values. The sampling switch SW is for example a switching circuit consisting of a MOS transistor such as CMOS transmission gate.
The sampling and holding circuit corresponds to a circuit shown in FIG.
18
(
a
) wherein the number of inputs is reduced to one. Since Cin and Cf are equal to each other, Vout=−Vin. At first the sampling switch SW is closed so as to sample the input signal. When SW is opened, an inverted voltage of the input voltage at the time is output from the ouput terminal The voltage is held until the sampling switch SW is closed. Accordingly, a sampling and holding circuit is realized.
An analog digital multiplication circuit using the above analog calculation circuit is shown in FIG.
20
. Vin is an input voltage, Vref is the reference voltage and Vref=Vdd/2=Vb. MUX
1
to MUX
n
are multi-plexers for switching capacitances having the first input terminals connected to V
1
, the second input terminals connected to Vref and output terminal connected to C
1
to C
n
, respectively. Control signals d
1
to d
n
are input to the multi-plexers MUX
1
to MUX
n
, respectively. Vin is selected to be input to C1 when di (i=1 to n) is “1”, and Vref is selected when di (i=1 to n) is “0”.
The capacitances C
1
to C
n
have capacity ratios that are powers of “2”, as defined by formula (5)
C
N
=2C
N−1
= . . . =2′C
H−i
= . . . =2
n−1
C
1
(5)
The formula for holding electrical charge is defined by equation (6).
∑
i
=
1
n
C
i
d
i
(
V
IN
-
Vb
)
+
∑
i
=
1
n
C
i
(
1
-
d
i
)
(
V
ref
-
Vb
)
+
Cf
(
Vout
-
Vb
)
=
0
(
6
)
The output voltage Vout is defined by formula (7), wherein Vref=Vb.
Vout
=
-
1
Cf
∑
i
-
1
n
C
i
d
i
V
i
n
=
C
1
Cf
V
i
n
∑
i
-
1
n
2
n
-
i
d
i
(
7
)
Vin multiplied by a binary number on n-bits corresponding to d
1
to d
n
is obtained as Vout. Therefore, a multiplication circuit for multiplying an analog data by a digital data is realized.
Various analog calculation circuits can be constructed by the above analog calculation circuit. The analog calculation circuit is a voltage driven type, so the electrical power consumption is very low. The circuit is easy to incorporate within an LSI. Various circuits other than the filter circuit (ADF: analog digital filter) can be realized using the sampling and holding circuit, multiplication circuit and adder above.
The above analog calculation circuit has a calculation error due to an error of
Shou Guoliang
Suzuki Kunihiko
Zhou Changming
Armstrong Westerman & Hattori, LLP
Callahan Timothy P.
Englund Terry L.
Yozan Inc.
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