Filter circuit for communication

Details Filter circuit for communication Filter circuit for communication

1999-09-24

2002-12-31

Mai, Tan V. (Department: 2787)

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

Reissue Patent

active

RE037953

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a filter circuit for communication, especially to a matched filter effective for a spread spectrum communication system for the mobile cellular radio and wireless LAN.
BACKGROUND OF THE INVENTION
A matched filter is a filter for judging the identification between two signals. In the spread spectrum communication, each user who receives a signal processes a received signal by a matched filter using spreading code allocated for the user to as to find a correlation peak for acquisition and holding.
Here, assuming that a spreading code is d(i), sampling interval is &Dgr;t, a length of spreading code is N, a received signal before a time t is x(T-i&Dgr;t), a correlation output y(t) of matched filter is as in formula (1). In formula (1), d(i) is a data string of 1 bit data.
y
⁡
(
t
)
=
∑
i
=
0
N
-
1
⁢
d
⁡
(
i
)
⁢
x
⁡
(
t
-
i
⁢
 
⁢
Δ
⁢
 
⁢
t
)
(
1
)
A conventional matched filter circuit is described here. In an accumulation circuit of a digital matched filter in
FIG. 16
, digitized input signal X is held in a shift register SFT-REG and shifted, then, a multiplier registered in a register REG is multiplied to the input signal on the predetermined sample timing by a plurality of digital multiplying portions DM. The outputs of multiplying portions are added by the digital adder DAD. These operations correspond to the formula (1). For the acquisition, double or higher order of sampling is necessary. In such a case, the circuit in
FIG. 16
is plurally structured. Consequently, the size of the whole circuit was large and consumed much electric power. It is a serious defect. Though a circuit of SAW device was used, the total circuits cannot be incorporated within one LSI and S/N ratio was low.
The applicant of the present invention proposes a matched filter circuit by an analog circuit in FIG.
17
. The electric power consumption was reduced by a circuit with a multiplier and an adder of voltage driven type using a capacitive coupling. However, a digital output is also necessary as an output of a matched filter because conventional digital communication will be also used for the present.
SUMMARY OF THE INVENTION
The present invention solves the above conventional problems and has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption.
In a matched filter circuit according to the present invention, the function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.
It is possible to use a circuit of rather low speed as an A/D converting circuit by the matched filter circuit according to the present invention. Therefore, it is profitable considering the cost, yield and electric power consumption.


REFERENCES:
patent: 4507746 (1985-03-01), Fletcher, Jr.
Dual 64-TAP, 11 Mcps Digital Matched Filter/Correlator STEL-3310, Stanford Communications, 1990.*
Tachika et al, A Development Conditions and Its Technical Issue of Digital Matched Filters in Spread-Spectrum Communication Systems, Technical Report of IEICE, STT92-21, 1992.*
Povey et al, “Simplified Matched Filter Receiver Designs for Spread Communications Applications,” Electronics & Communications Engineering Journal, vol. 5, No. 2, Apr. 1, 1993.*
Nauerz, “The Suitability of Modern CMOS Grate Array Circuits as Correlations and Matched Filters for Spread-Spectrum Signals”, Crisis Communications, vol. 2 of 3, Oct. 1987.*
Tanaka et al., “Development of Low Power Consumption LSI for SS Communication ,” Technical Report of IEICE, STT95-77, Oct. 1995.*
Ogawa et al, “Development of 1 Chip Ss Communication LSI Using Digital Matched Filters,” Technical Report of IEICE, ISEC 94-42, SST94-95, Dec. 1994.

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