Filter circuit

Details Filter circuit Filter circuit

1999-02-26

2001-10-09

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

C327S552000, C708S317000

Reexamination Certificate

active

06300823

ABSTRACT:

DETAILED DESCRIPTION OF THE INVENTION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a filter circuit, particularly to an analog-digital filter for multiplying an analog input signal by a digital multiplier.
2. Prior Art
In general, an analog filter consumes less electrical power than a digital filter, however, the analog filter has low controllability and accuracy as well as large deviation due to deviation of electronic elements. Usually, an analog signal is converted into a digital signal by an analog to digital (A/D) converter, and the digital signal is processed by a digital filter consisting of a digital signal processor (DSP). The processed digital data is converted again into an analog signal. Such digital filter has a high flexibility and high performance as a high order filter, however, the digital filter is of a large system size, high cost, large power consumption and low speed.
The inventors of the present invention proposed an analog digital filter (ADF) for multiplying an analog signal by a digital data. The analog input signal is directly controlled by a digital signal so that a multiplication of the analog signal by a digital signal is performed. The ADF is good in the calculation accuracy, in filter characteristics, in power consumption and in process speed.
FIG. 19
is circuit diagram of the ADF. In
FIG. 19
,
110
O
to
110
L-1
are sampling and holding circuits (S/H),
120
O
to
120
L-1
are multiplier registers and
130
O
to
130
L-1
are multiplication circuits (MUL). Sampled signals output from the sampling and holding circuits
110
O
to
110
L-1
are multiplied in the multiplication circuits
130
O
to
130
L-1
by digital data supplied from the multiplier registers
120
O
to
120
L-1
.
140
is an adder for summing up outputs of the multiplication circuit
130
O
to
130
L-1
.
150
is a scaler for multiplying an output of the adder
140
by a multiplier (coefficient). The output y(n) of the adder
140
is given by the following formula (1).
y
⁡
(
nT
)
=
∑
k
=
0
L
-
1
⁢
h
⁡
(
kT
)
·
x
⁡
(
nT
-
kT
)
(
1
)
Here, h: filter coefficient,
x: input signal,
n: an integer (−∞ to ∞),
T: sampling interval, and
L: tap length.
Each of the multiplication circuits
130
O
to
130
L-1
, the adder
140
and the scaler
150
includes an analog amplifier based on a CMOS inverter and a capacitance. The electric power is scarcely consumed because only little power is consumed in the CMOS inverters. The power consumption is not influenced by the frequency of the operation.
In order to prevent an over-range, the input signals to the multiplication circuits
130
O
to
130
L-1
are multiplied by
1
2
N
-
1
,
and the input of the adder
140
is multiplied by
1
L
.
The scaler multiplies the output of the adder
130
by 2
N-1
·L.
The filter coefficient h to be set in the multiplier registers
120
to
120
L−1 is quantized into N-bit data (8 bit, for example), that is, (−2
N-1
−1) to (2
N-1
−1). The filter coefficient is multiplied by M before the quantization for improving the accuracy.
FIG.
20
(
a
) show the filter coefficient and FIG.
20
(
b
) shows M times h (=M×h) so that the maximum value of the filter coefficient is limited to (2
N-1
31 1) and stored in the registers
120
O
to
120
L-1
. Then, the output of the adder
140
is multiplied by
1
M
.
However, the absolute value of (=M×h) may be different in the positive and negative sides from each other as shown in FIG.
20
(
b
). The resolution of N-bit is not fully utilized.
Furthermore, a filter circuit of smaller circuit size and of less electrical power consumption is required.
SUMMARY OF THE INVENTION
The present invention has an object to provide a filter circuit of high accuracy.
The present invention has another object to provide a filter circuit of a small circuit size.


REFERENCES:
patent: 5872466 (1999-02-01), Shou et al.

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