Filter arithmetic device

Image analysis – Image compression or coding – Interframe coding

Reexamination Certificate

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Details

C382S260000, C375S240130, C708S300000

Reexamination Certificate

active

06668087

ABSTRACT:

TECHNICAL FIELD
The present invention relates to filter operation apparatus which are used in image coding methods.
BACKGROUND ART
As the international standard systems as to image coding, there are MPEG (Moving Picture Experts Group) according to ISO (International Standardization Organization), ITU-T (International Telecommunication Union-Telecommunication Sector) recommendation H.261 and the like. Although the use of MPEG is increasing in recent years, the conventional H.261 is still utilized as always in the present circumstances. That is, both of the systems exist together at present. Therefore, filter operation apparatus which can be used in both of the systems are required.
Initially, these systems are briefly described.
In the coding method according to MPEG of ISO, DCT (Discrete Cosine Transform) which performs orthogonal transform as a compression method utilizing a spatial correlation is used for bidirectional motion compensation inter-frame prediction as a method utilizing a temporal correlation. Half-pixel motion compensation used in this method is a simple method of averaging two pixels when the position of a pixel to be predicted is between the two pixels and averaging four pixels when the position is among the four pixels. Accordingly, the half-pixel motion compensation not only increases the prediction accuracy but also has a function of a spatial low-pass filter. Further, when the four pixels are averaged, there are some cases where an average pixel value in the horizontal direction is obtained and then an average pixel value in the vertical direction with respect to the obtained average pixel value is obtained as an average of the four pixel values.
In the coding method according to ITU-T recommendation H.261, compression methods utilizing the spatial correlation or temporal correlation are used as in MPEG system. However, in this coding method, an intra-loop filter, i.e., a spatial low-pass filter is used to avoid the situation that the distortion occurring due to the quantization is stored in a prediction memory, whereby the degradation in image quality is increased and the prediction efficiency is decreased.
In the processing of this intra-loop filter, the weighting is performed according to the positions of pixels, as shown in FIG.
21
.
To be specific, a pixel value P of a pixel p in each region shown in
FIG. 21
obtains a new pixel value P′ in a following manner.
As for a pixel value P of a pixel p in a region
2100
,
P
′=16×(
P
/16)  (1)
As for a pixel value P of a pixel p in a region
2101
,
P
′=((4
×A
)+(8
×P
)+(4
×B
))/16  (2)
As for a pixel P in a region
2102
,
P′=(
A
+(2
×B
)+
C
+(2
×D
)+(4
×P
)+(2
×E
)+
F
+(2
×G
)+
H
))/16  (3)
In the expressions (1)~(3), a~h each denote a pixel adjacent to each of the pixels p shown in FIG.
21
and A~H each denote a pixel value of each of the pixels a~h shown in FIG.
21
. The processing for the weighting is performed twice, i.e., in the horizontal direction and vertical direction.
Usually, the conventional filter operation apparatus which realizes the filter processing of the above-mentioned coding method according to MPEG of ISO and coding method according to ITU-T recommendation H.261 in an apparatus is constructed so that a part of the apparatus is shared in the filter processing of these two coding methods, thereby avoiding the increase in the scale of hardware. If each of parts associated with these two coding methods is independently provided in one apparatus, the scale of the hardware is adversely increased.
The structure and operation of the conventional filter operation apparatus X are briefly described with reference to drawings.
FIG. 14
is a diagram simply illustrating a structure of the conventional filter operation apparatus X having a horizontal half-pixel motion compensation and horizontal. intra-loop filtering means
1400
and a vertical half-pixel motion compensation and vertical intra-loop filtering means
1401
.
FIG. 15
is a block diagram illustrating a structure of the horizontal half-pixel motion compensation and horizontal intra-loop filtering means
1400
.
FIG. 16
is a block diagram illustrating a structure of the vertical half-pixel motion compensation and vertical intra-loop filtering means
1401
.
Initially, the structure of the horizontal half-pixel motion compensation and horizontal intra-loop filtering means
1400
is described with reference to FIG.
15
. The horizontal half-pixel motion compensation and horizontal intra-loop filtering means
1400
comprises a first pixel delay means
1500
for delaying an input pixel D
21
for a predetermined period and outputting a delayed pixel, a multiplication means
1501
for multiplying the input pixel D
21
by two and outputting a multiplied pixel, a first selection means
1502
for selectively outputting one of the input pixel D
21
and the pixel which is obtained by multiplying the input pixel D
21
by two by the multiplication means
1501
in accordance with a mode switch signal S
21
for switching the mode between “half-pixel motion compensation mode” and “intra-loop filtering mode”, a second selection means
1503
for selectively outputting one of “0” and the output of the first pixel delay means
1500
in accordance with a first intra-loop filter control signal S
22
, a third selection means
1504
for selectively outputting one of the output of the first selection means
1502
and the output of the second selection means
1503
in accordance with a half-pixel motion compensation control signal S
23
, a first addition means
1505
for adding the output of the second selection means
1503
and the output of the third selection means
1504
and outputting output data D
22
, a second pixel delay means
1506
for delaying the output signal of the first addition means
1505
for a predetermined period and then outputting output data D
23
, a fourth selection means
1507
for selectively outputting one of the input pixel D
21
and the output signal of the second pixel delay means
1506
in accordance with a second intra-loop filter control signal S
24
, a second addition means
1508
for adding the output of the second pixel delay means
1506
and the output of the fourth selection means
1507
and outputting output data D
24
, and a third pixel delay means
1509
for delaying the output signal of the second addition means
1508
for a predetermined period and then outputting output data D
25
.
Next, the operation of the horizontal half-pixel motion compensation and horizontal intra-loop filtering means
1400
is described with respect to the cases of half-pixel motion compensation and intra-loop filtering, respectively. Assume that the first pixel delay means
1500
, the second pixel delay means
1506
, and the third pixel delay means
1509
each delay the data for one clock.
A format of input data in the case of half-pixel motion compensation is described with reference to FIG.
3
. As shown in FIG.
3
(
a
), the format of input data which are subjected to the horizontal processing for generating 8×8 half-pixels in the horizontal processing consists of 9×9 pixels. As shown by arrows in FIG.
3
(
a
), the processing is performed successively from left to right and from top to bottom on a two-dimensional space.
To be more specific, the processing is performed in the order of A→B→C→ . . . →I→J→K→ . . . →Z as shown in FIG.
3
(
a
). Timing charts of
FIGS. 17
show this operation in more detail. In
FIGS. 17
, S
21
denotes a control signal for controlling the first selection means
1502
shown in
FIG. 15
to output “a”. S
22
denotes a control signal for controlling the second selection means
1503
shown in
FIG. 15
to output “b”. S
23
denotes a control signal for controlling the third selection means
1504
shown in
FIG. 15
to output “b”. S
24
denotes a control signal for controlling the fourth se

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