Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-06-21
2004-01-27
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S707000, C438S781000
Reexamination Certificate
active
06683006
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a film forming method to simplify steps in forming a pattern on a semiconductor device. More specifically, the present invention relates to a film forming method using a silylation process and a film forming apparatus.
2. Description of the Related Art
In a manufacturing step in a process of a semiconductor device an inter-layer insulation film is formed on a wafer. In particular, for example, a material of fluoropolymer type and a siloxane type are used as an insulation film material in order to realize low dielectric constant.
For example, the inter-layer insulation film is formed with SOD (Spin on Dielectics, coating method) system. In the SOD (Spin on Dielectric) system, a film is spin-coated on a wafer and an insulation film is formed with performing processes like chemical process or heating process on the wafer. A hard mask made of silicon dioxide (SiO
2
) is formed on the coating film and resist is coated thereon, followed by pattern drawing on the coated resist and the pattern drawing is performed further on the insulation film using the patterned resist as a mask.
Then, after forming a barrier metal layer, copper (Cu) conductor is embedded and a surface thereof is planarized with performing a Chemical Mechanical Polishing (CMP) using the barrier metal layer as a stopper.
Incidentally, in recent years, a semi-conductor device has become more precise and higher resolution is required when drawing a pattern on a wafer. For this reason, there is an increasing demand for higher quality in the lithography technology used in the wafer processing and a resist material.
A multi-layer resist process is used as a technology to cope with such situation. The multi-layer resist process is drawing patterns on an inter-layer insulation film and a hard-mask with coating a plurality of layers of the resist, and drawing patterns on the layers of the resist one by one from the top. Although the aforementioned method has an advantage that a minute pattern can be formed precisely for it is possible to reduce the thickness of a resist layer in an upper layer, there is a problem that a special resist material is required.
To solve such problem, a silylation processing is used. This method selectively introduces silicon atoms solely onto a desired part of the resist with silylation process after exposure so that oxygen plasma etching resistance is provided. After the process the micro-pattern is formed. Additionally, this method allows commercially available resists, having outstanding performances in both sensitivity and resolution, to be used as they are. The method can also be generally applied to various forms of exposure such as using electron beam and X-rays as well as light exposure.
A film forming method using a common silylation processing will be explained below with reference to drawings.
FIG. 11
is a schematic view showing a conventional silylation processing, and
FIG. 12
is a flow chart explaining processing steps as illustrated in FIG.
11
.
After an inter-layer insulation film
301
is spin-coated on the wafer W with a coating apparatus as illustrated in
FIG. 11A
(Step
1
), oxidation silicon is coated as a hard mask
302
on the insulation film as illustrated in FIG.
11
B. Next, a resist
303
is coated on the hard mask as illustrated in
FIG. 11C
(Step
2
), then an upper layer resist
304
as a silylated resist is coated thereon thinly compared with the resist
303
as illustrated in
FIG. 11D
(step
3
). After that, the wafer undergoes a pre-baking process (step
4
), and the upper layer resist
304
is exposed with an aligner as illustrated in
FIG. 11E
(Step
5
). Then the wafer undergoes a post-baking process (Step
6
), followed by a silylation process of exposing to an organic gas containing, for example, an organic silane such as a halogenation alkyl silane having Si atoms and the like, for a predetermined time period as illustrated in
FIG. 11F
(Step
7
) and un-exposed portion becomes a silylated layer by silylation reaction. Thereafter, the resist is hardened in an UV apparatus (Step
8
). Then, the upper layer resist
304
is etched except for the silylated layer and a micro-pattern is formed as illustrated in
FIG. 11G
(Step
9
). After the upper layer resist
304
and the lower layer resist
303
are removed simultaneously as illustrated in
FIG. 11H
(Step
10
), a barrier metal is coated thereon and a barrier metal layer is formed as illustrated in
FIG. 11I
(Step
11
). Then Cu is embedded with plating the substrate with Cu as illustrated in
FIG. 11J
(Step
12
), and the surface is planarized with Chemical Mechanical Polishing (CMP) as illustrated in
FIG. 11K
(Step
13
).
However, in this process, the resist film for silylation has to be coated on the layer of the resist and has to be removed again, causing increase in the number of steps, leading to a complication. In addition, a hard-mask is required to be coated on the inter-layer insulation film that also is a cause of the steps becoming complicated.
SUMMARY OF THE INVENTION
The present invention is made from the above-described point of view and the object thereof is to provide a film forming method enabling a resist to be used as a hard mask with performing a silylation process thereon. Further, an object of the present invention is to provide a film forming method that improves throughput with enabling the resist film for silylation to be used as a CMP stopper instead of removing thereof, with using an assisting technology such as an electron beam and the like and hardening not only the surface of the resist but also the inside thereof and simplifying the manufacturing steps.
To attain the aforesaid objects, the present invention has the steps of (a) coating a resist film for silylation on a surface of an insulation film of a semiconductor substrate, (b) exposing a pattern on the resist film for silylation, (c) performing a silylation process with causing the resist film for silylation chemically react with a compound including silicon and forming a silylated layer, (d) etching the insulation film using the silylated layer as a mask, and (e) forming a metal film on the silylated layer without removing the silylated layer used as the mask.
According to the aforesaid structure, since the resist for silylation is applied directly onto the insulation film and being used as a hard mask, patterning the insulation film with a single layer of the resist film for silylation becomes possible. Moreover, the silylated resist can also be used as a CMP stopper without being removed. The manufacturing steps can be simplified with this method.
Also, in the present invention, the mask is formed with dry etching the silylated layer in the step (d). The step is again simplified since it is not required to form a hardmask beforehand.
Additionally, in the present invention, a step of hardening the silylated layer with performing an electron beam processing or an ultraviolet ray processing may be provided before the step (d), or a step of hardening the silylated layer with performing electron beam processing or ultraviolet ray processing may be provided after the step (d). The silylated layer is able to be used as a CMP stopper thereafter since the inside as well as the surface of the silylated layer can be hardened.
Further, the present invention has a step of planarizing the film surface with performing a chemical mechanical polishing using the silylated layer as a stopper after the step (e). The step is further simplified since the silylated layer can be used as a CMP stopper without removing thereof.
The present invention has a film forming apparatus disposed adjacent to an aligner selectively exposing a resist film for silylation, an etching apparatus etching an insulation film using a silylated layer as a mask and a metal film forming apparatus forming a metal film on the silylated layer being used as the mask without removing thereof, comprising a resist film for silylation forming portion forming a resist film fo
Iwashita Mitsuaki
Konishi Nobuo
Ghyka Alexander
Tokyo Electron Limited
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