Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1998-06-16
2000-10-10
Bowers, Charles
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438 25, 438 26, 438 51, 438 64, H01L 2148, H01L 2150
Patent
active
061301108
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The invention relates to a method of making a film carrier tape, a method of making a tape carrier semiconductor device assembly, a method of making a semiconductor device, a film carrier tape, a semiconductor device, a mounted board, and an electronic device, and particularly to Chip Size/Scale Package (CSP) fabrication technology and mounting technology for CSP.
BACKGROUND ART
There is no formal definition of Chip Size/Scale Package (hereinafter called CSP), but generally this refers to a semiconductor package (IC package) in which the package size is the same as or only very slightly larger than the chip size. The development of CSP technology is very important for promoting high-density mounting.
One prior art publication relating to CSP is International Publication WO95/08856. In this publication, the method is adopted in which a lead frame is mounted on a lead frame support (special-purpose jig), and the leads are cut respectively (one by one) by a special tool, while at the same time the severed leads are bent downward, and are connected to bonding pads of the IC chip.
With this method, a special jig or equipment is required, and additionally leads may easily be made bent during the bonding to the IC chip by the cutting of the leads.
SUMMARY OF THE INVENTION
The methods and systems of this invention includes steps for making a film carrier tape. The steps include forming a conducting foil on an insulating film and forming from the conducting foil a conductor pattern having a plurality of leads, each leads with one end formed as a free end and with an electrical connection portion on the free end for connection to at least one semiconductor chip. There are also link portions for linking together the plurality of leads and the link portions are provided within a mounting area of the semiconductor chip. A frame is electrically connected to all of the leads through the link portions. The steps also include plating the conductor pattern and stamping out the link portions, thereby electrically isolating each of the plurality of leads.
According to the invention, prior TAB (Tape Automated Bonding) production line and existing technology can be used, reducing the burden for new equipment and the development of special technology.
The most important extremities of the leads (the portions for connection to a semiconductor chip; the so-called fingers) are not connected to a frame, but are free, (that is to say, are terminated), and are not subject to any process at all until the bonding process. In the bonding process, since the fingers are already terminated, cutting is not required, and there is no risk of shear stress. That is to say, from the time the pattern is formed, no external load is applied to the leads, therefore, bending of the leads is prevented. As a result, the positioning of the leads and the bonding pads of the semiconductor chip can be carried out accurately.
However, in order to carry out, for example, electroplating in a single operation on the plurality of leads formed on the insulating film of polyimide or the like, all of the leads must inevitably be electrically connected to the frame.
For this reason, the invention has a plurality of link portions disposed within the mounting area of the semiconductor chip. The link portions link a plurality of leads within the mounting area of a semiconductor chip, and thus electrical connection of the leads to the frame is achieved through these link portions. By means of this, a voltage is applied to the frame. For example, one electrode (generally the anode) is connected to the frame to allow electroplating to be applied to the entire conductor pattern together, including the leads.
Next, the link portions, which are no longer needed, are die-stamped out and removed together with the insulating film, thereby electrically isolating the leads from each other. This die-stamping-out can be carried out in single operation, and does not complicate the process. Besides, the link portions are disposed within the mounting area of a s
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patent: 5075252 (1991-12-01), Schendelman
patent: 5107325 (1992-04-01), Nakayoshi
patent: 5231303 (1993-07-01), Kasahara
Michael Pecht, ed. Handbook of Electronic Package Design, Marcel Dekker: New York, pp. 187-192 and 256-257, 1991.
Bowers Charles
Kielin Eric J
Seiko Epson Corporation
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