Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-10-27
2002-07-02
Clark, Jasmine J. B. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S673000, C257S783000, C257S774000
Reexamination Certificate
active
06414382
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument, and particularly to chip size package (CSP) fabrication technology and mounting technology for CSP.
BACKGROUND ART
There is no formal definition of chip size/scale package (CSP), but generally this refers to an IC package in which the package size is the same as or only very slightly larger than the chip size. The development of CSP technology is very important for improving packaging density.
CSP differs from a quad flat package (QFP) having outer leads only around the periphery of the package, in having external connection terminals arranged in a plane, and capable of being surface mounted. More specifically, a conventional CSP comprises a polyimide substrate on which wiring is formed, external connection terminals formed on this wiring, and a semiconductor chip attached on the surface of the polyimide substrate opposite to that on which the external connection terminals are formed, and the wiring is connected to the electrodes of the semiconductor chip. Moreover, solder resist is applied to the surface of the wiring, and oxidation of the wiring is prevented.
When solder resist adheres not only to the wiring but also to the external connection terminals, during mounting bad electrical connections occur. Because of this, solder resist adhering to the external connection terminals must be removed, or the solder resist must be applied to avoid the external connection terminals, complicating the process.
The present invention seeks to solve the above mentioned problems, and has as its object the provision of a film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument to which CSP technology is applied, but in which the application of solder resist to the surface is avoided.
DISCLOSURE OF THE INVENTION
The film carrier tape of the present invention comprises:
a substrate material having flexible and insulating properties; and
a wiring pattern formed on one of sides of the substrate material, the wiring pattern including a plurality of leads connected to a semiconductor element and a pad integrally formed with each of the leads for an external connection terminal formed thereon, each of the leads being adhered to the substrate material on a whole surface facing the substrate material, and the substrate material having an opening at a position corresponding to the pad for forming the external connection terminal.
According to the present invention, since an opening is provided beforehand, external connection terminals can be provided on the surface opposite to that on which the wiring pattern is formed, connected to the wiring pattern through the opening. Therefore, it is not necessary to apply solder resist to the wiring pattern while avoiding external connection terminals. Moreover, if a semiconductor element is disposed on the surface on which the wiring pattern is formed, the wiring pattern is not exposed, and therefore the application of a solder resist can be omitted.
In this way, a semiconductor element is disposed on the surface of the substrate material on which the wiring pattern is formed, and a structure for connection to the mounted board is provided on the opposite surface, and thereby an ultracompact semiconductor device can be obtained.
The opening is formed to correspond to the pads, and therefore the pads are independent of the substrate material. Therefore, the incidence of stress between the pads and the substrate material can be reduced.
In the present invention, the connection portion with the semiconductor element by the leads, being the most important, is adhered to the substrate material. Therefore, from the time when the film carrier tape is fabricated until the subsequent processes (semiconductor assembly fabrication, semiconductor device fabrication), that is to say, after the time of pattern formation, if a lead is subjected to an external load, it is supported by the substrate material and bending of the leads can be prevented. There is therefore the advantage that the positioning of the leads and the bonding pads of the semiconductor element can be carried out accurately. In particular, in an embodiment in which very fine processing technology is required, such as CSP, the larger the free region of the leads the more likely bending is to occur, but if as in the present invention the connection portion of the leads is adhered to the substrate material, handling is made easier.
Furthermore, in the present invention, the wiring pattern including the leads is formed on the surface of the substrate material, and part of the leads forms a connection portion with the semiconductor element. Therefore, the region other than the connection portion of the leads is also formed on the surface of the substrate material, so that compared with the structure in which the connection portion only is a separate member, it is possible to apply thermal stress and the like evenly, and an improvement in the reliability of the connection portion can be achieved.
In the present invention, since a semiconductor element is connected to part of the wiring pattern formed on the substrate material, the ingress of moisture can be prevented, compared to the case in which the semiconductor element is connected to the wiring pattern by a separate member and filled with resin. In particular, for a CSP, since the package is close to the electrodes, the present invention is efficacious.
The film carrier tape may further comprise projections formed on the wiring pattern on the substrate material, of the same material as the wiring pattern and used for connection to the semiconductor element.
Through the projections formed on the wiring pattern on the substrate material, an electrical connection between the electrodes formed on the semiconductor element and the wiring pattern can be obtained, and as far as possible a conventional TAB (Tape Automated Bonding) production line and existing technology can be used, enabling the burden of equipment and the burden of the development of special technology to be lightened.
Since the projections and wiring pattern are formed of the same material, the coefficient of thermal expansion is the same, and when a thermal stress is applied to them, no thermal stress occurs between them, and therefore the film carrier tape and a semiconductor assembly or semiconductor device formed using the same can have its thermal reliability improved. Since the oxidation-reduction potential is the same, even if humidity stress is applied, no local cells form, and therefore the reliability with respect to humidity can also be improved.
The film carrier tape of the present invention comprises:
a substrate material;
a wiring pattern formed on one of sides of the substrate material; and
a stress relieving portion provided on the one of sides of the substrate material, in a region corresponding to a position for forming at least an external connection terminal and avoiding a connection portion of the wiring pattern for connection to a semiconductor element.
In this film carrier tape, a conductive resin may be provided at least on the connection portion. By means of this conductive resin, the electrical connection with the semiconductor element is achieved.
In particular, it is preferably a film carrier tape such that the connection portion is of convex form.
The semiconductor assembly of the present invention comprises:
a substrate material having flexible and insulating properties;
a wiring pattern formed in adherence with one of sides of the substrate material;
a plurality of semiconductor elements disposed on a surface of the substrate material on which the wiring pattern is formed;
a connection portion forming part of the wiring pattern, electrically connected to each of the semiconductor elements, and adhered to the substrate material;
a plurality of pads forming part of the wiring pattern, eac
Clark Jasmine J. B.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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