Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-07-20
2001-10-09
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C324S765010, C361S767000, C361S777000
Reexamination Certificate
active
06300577
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the structure of a film carrier and a method of collectively burn-in testing IC chips assembled on a base film of the film carrier by the TAB (Tape Automated Bonding) technique.
2. Description of the Background Art
FIG. 12
is a top view showing a top structure of a conventional film carrier.
FIG. 13
is a bottom perspective view showing a bottom structure of the film carrier of
FIG. 12
as seen through from above. The film carrier comprises a base film
101
provided with a plurality of sprocket holes
102
arranged at regularly spaced apart intervals in the longitudinal direction of the base film
101
. IC chips
104
are assembled on the base film
101
by the TAB technique. A plurality of test pads
103
in corresponding relation to a plurality of pads (not shown) of the IC chips
104
are formed on the base film
101
. The test pads
103
and the pads of the IC chips
104
are connected to each other through leads
106
formed on the top surface of the base film
101
, respectively. All of the test pads
103
are connected to an interconnect line
105
formed on the top surface of the base film
101
. The interconnect line
105
is provided for electroplating the leads
106
and generally known as a plating line. A predetermined potential is applied from the interconnect line
105
through the test pads
103
to the leads
106
in a predetermined metal solution to electroplating the surfaces of the leads
106
for improvements in corrosion resistance of the leads
106
.
For mounting the IC chips
104
on a circuit board, the leads
106
are severed at some midpoints, and the severed leads
106
are connected to electrodes of the circuit board. In general, tests are carried out on the IC chips
104
prior to the severing of the leads
106
, that is, with the IC chips
104
assembled on the base film
101
. One of the tests includes a burn-in test to be conducted on the IC chips
104
.
FIG. 14
illustrates a method of burn-in testing the IC chips
104
. First, the film carrier is severed into pieces each including an IC chip
104
, and connecting portions between the interconnect line
105
and the test pads
103
are cut off. Then, the pieces of the film carrier each of which includes an IC chip
104
are mounted in sockets
107
installed on a burn-in board
108
. Next, the burn-in board
108
is loaded into a burn-in apparatus
109
. Thereafter, a predetermined power supply potential and a predetermined ground potential are applied from the burn-in apparatus
109
to predetermined ones of the test pads
103
.
However, such a conventional film carrier is disadvantageous in that the burn-in testing of the IC chips assembled on the base film requires the burn-in board and the sockets, to result in increased costs.
Further, it takes time to mount the severed pieces of the film carrier each including an IC chip into the sockets. This causes prolonged time for preparation for the burn-in test.
Additionally, the limited capacity of the burn-in apparatus imposes limitations on the number of burn-in boards to be loaded in the burn-in apparatus at one time and accordingly on the number of IC chips to be subjected to the burn-in test at one time.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a film carrier comprises: a base film; a plurality of test pads provided on the base film in corresponding relation to a plurality of pads of each IC chip assembled on the base film; a first interconnect line provided on the base film and connected commonly to the plurality of test pads; and a second interconnect line provided on the base film and connected commonly to the plurality of test pads, the second interconnect line being electrically insulated from the first interconnect line except where the plurality of test pads are provided.
Preferably, according to a second aspect of the present invention, in the film carrier of the first aspect, at least one of the first and second interconnect lines is a plating line for electroplating leads for providing connection between the test pads and the pads.
Preferably, according to a third aspect of the present invention, in the film carrier of the first aspect, the plurality of test pads are selectively formed through between first and second major surfaces of the base film, the first interconnect line being provided on the first major surface of the base film, the second interconnect line being provided on the second major surface of the base film.
Preferably, according to a fourth aspect of the present invention, in the film carrier of the third aspect, the first and second interconnect lines are connected to the test pads so as to be in two-dimensionally non-overlapping relationship with each other at connecting portions between the first and second interconnect lines and the test pads.
A fifth aspect of the present invention is intended for a method of collectively burn-in testing IC chips of a film carrier, the film carrier including a base film, a plurality of test pads provided on the base film in corresponding relation to a plurality of pads of each of the IC chips assembled on the base film, a first interconnect line provided on the base film and connected commonly to the plurality of test pads, and a second interconnect line provided on the base film and connected commonly to the plurality of test pads, the second interconnect line being electrically insulated from the first interconnect line except where the plurality of test pads are provided. According to the present invention, the method comprises the steps of: (a) severing first connecting portions between the first interconnect line and other than one of the test pads which is associated with a first pad, the first pad being one of the plurality of pads which is to receive a predetermined first potential; (b) severing second connecting portions between the second interconnect line and other than one of the test pads which is associated with a second pad, the second pad being one of the plurality of pads which is to receive a predetermined second potential; and (c) applying the first potential to the first pad through the first interconnect line and applying the second potential to the second pad through the second interconnect line.
Preferably, according to a sixth aspect of the present invention, in the method of the fifth aspect, the first and second interconnect lines are connected to the test pads so as to be in two-dimensionally non-overlapping relationship with each other at connecting portions between the first and second interconnect lines and the test pads; and the first and second connecting portions are severed by forming through holes extending from a first major surface of the base film to a second major surface thereof in the first and second connecting portions, respectively.
Preferably, according to a seventh aspect of the present invention, the method of the fifth aspect further comprises the steps of: (d) winding the film carrier onto a reel, the step (d) being performed after the steps (a) and (b) and before the step (c); and (e) loading the reel into a burn-in apparatus, wherein the first and second potentials are applied from a potential supply portion to the first and second interconnect lines, the potential supply portion being connected to the first and second interconnect lines at an end of the film carrier.
In accordance with the first aspect of the present invention, the film carrier includes the first and second interconnect lines which are electrically insulated from each other except where the test pads are provided. Thus, the connecting portions between the first and second interconnect lines and each of the test pads may be selectively severed to leave the connection between the first interconnect line and a test pad or the connection between the second interconnect line and a test pad. This allows different potentials to be applied to pads of the IC chip through the first and second interconnect lines and the test pads connected t
Gaffin Jeffrey
Mitsubishi Denki & Kabushiki Kaisha
Norris Jeremy
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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