Static information storage and retrieval – Plural shift register memory devices
Patent
1989-04-03
1993-11-30
Bowler, Alyssa H.
Static information storage and retrieval
Plural shift register memory devices
365221, 36518904, G11C 700, G11C 1900, G11C 2100
Patent
active
052671917
ABSTRACT:
The subject invention is a FIFO memory system and method for buffering data between two data busses. The system comprises a RAM memory, write and read pointer registers, an offset generator, a programmable offset register, and a comparator. The write pointer register stores the address of the next data element to be written into the RAM memory, and the read pointer register stores the address of the next data element to be read from the RAM memory. The offset generator compares the contents of the registers, and generates at an output thereof an offset signal representing the amount of memory space occupied. The programmable offset register provides a programmed offset signal. The comparator compares the offset signal and the programmed offset signal, and provides a ready signal when the offset signal is greater than or equal to the programmed offset signal.
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Bowler Alyssa H.
Foote Douglas S.
NCR Corporation
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