Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-01-02
2007-01-02
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S221000
Reexamination Certificate
active
10881985
ABSTRACT:
First-in first-out (FIFO) memory devices are configured to support all four of the following FIFO memory modes: (1) DDR write with DDR read, (2) DDR write with SDR read, (3) SDR write with DDR read and (4) SDR write with SDR read. These FIFO memory devices provide flexible x4N, x2N and xN bus matching on both read and write ports and enable data to be written and read on both rising and falling edges of the write and read clock signals. Custom flag generation and retransmit circuitry is also provided that can efficiently handle any width DDR write mode with any width SDR read mode or any width SDR write mode with any width DDR read mode.
REFERENCES:
patent: 5261064 (1993-11-01), Wyland
patent: 5365485 (1994-11-01), Ward et al.
patent: 5371708 (1994-12-01), Kobayashi
patent: 5546347 (1996-08-01), Ko et al.
patent: 5663910 (1997-09-01), Ko et al.
patent: 5860160 (1999-01-01), Narayana et al.
patent: 5978307 (1999-11-01), Proebsting et al.
patent: 5982700 (1999-11-01), Proebsting
patent: 5999478 (1999-12-01), Proebsting
patent: 6072741 (2000-06-01), Taylor
patent: 6094375 (2000-07-01), Lee
patent: 6115760 (2000-09-01), Lo et al.
patent: 6118835 (2000-09-01), Barakat et al.
patent: 6134180 (2000-10-01), Kim et al.
patent: 6147926 (2000-11-01), Park
patent: 6151273 (2000-11-01), Iwamoto et al.
patent: 6154418 (2000-11-01), Li
patent: 6154419 (2000-11-01), Shakkarwar
patent: 6201760 (2001-03-01), Yun et al.
patent: 6233199 (2001-05-01), Ryan
patent: 6240031 (2001-05-01), Mehrotra et al.
patent: 6240042 (2001-05-01), Li
patent: 6252441 (2001-06-01), Lee et al.
patent: 6259652 (2001-07-01), Heyne et al.
patent: 6263410 (2001-07-01), Kao et al.
patent: 6269413 (2001-07-01), Sherlock
patent: 6272065 (2001-08-01), Kim
patent: 6279073 (2001-08-01), McCracken et al.
patent: 6282128 (2001-08-01), Lee
patent: 6327216 (2001-12-01), Ryan
patent: 6330636 (2001-12-01), Bondurant et al.
patent: 6337809 (2002-01-01), Kim et al.
patent: 6337830 (2002-01-01), Faue
patent: 6338103 (2002-01-01), Kirihata
patent: 6339558 (2002-01-01), Ioki
patent: 6356506 (2002-03-01), Ryan
patent: 6377071 (2002-04-01), Wang et al.
patent: 6381194 (2002-04-01), Li
patent: 6381661 (2002-04-01), Messerly et al.
patent: 6381684 (2002-04-01), Hronik et al.
patent: 6400642 (2002-06-01), Mehrotra et al.
patent: 6411561 (2002-06-01), Ayukawa et al.
patent: 6438066 (2002-08-01), Ooishi et al.
patent: 6477110 (2002-11-01), Yoo et al.
patent: 6522599 (2003-02-01), Ooishi et al.
patent: 6546461 (2003-04-01), Au et al.
patent: 6671787 (2003-12-01), Kanda et al.
patent: 2001/0004335 (2001-06-01), Murakami
patent: 2001/0014053 (2001-08-01), Li
patent: 2001/0029558 (2001-10-01), Kobara et al.
patent: 2001/0054121 (2001-12-01), Proch et al.
patent: 2002/0048201 (2002-04-01), Garg
patent: 2001/0071332 (2002-06-01), Nishiyama et al.
patent: 2002/0089927 (2002-07-01), Fischer et al.
patent: 0 421 627 (1990-09-01), None
patent: 0 978 842 (2000-02-01), None
patent: 0820618 (1996-08-01), None
Invitation to Pay Additional Fees, Annex to Form PCT/ISA/206, Communication Relating to the Results of the Partial International Search, PCT/US02/26516, Oct. 13, 2003.
Au Mario Fulam
Duh Jiann-Jeng
Integrated Device Technology Inc.
Myers Bigel & Sibley & Sajovec
Nguyen Van-Thu
LandOfFree
FIFO memory devices having write and read control circuits... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with FIFO memory devices having write and read control circuits..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO memory devices having write and read control circuits... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3742794