FIFO memory controller for a digital video communications channe

Details FIFO memory controller for a digital video communications channe FIFO memory controller for a digital video communications channe

1992-05-08

1995-01-03

Dixon, Joseph L.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

377 41, 364DIG1, 3642443, 3642447, 3649336, 3649427, 326 35, 326105, G06F 1300

Patent

active

053793994

ABSTRACT:
A controller for a first in first out (FIFO) memory comprises detector logic for detecting any difference between the number of addresses in the memory into which data is written and the number of addresses in the memory from which data is read. Comparator logic connected to the detector logic generates a request data transfer signal in response to said difference becoming greater than or equal to a threshold. Threshold select logic connected to the comparator logic is responsive to data having first and second portions being written to the memory. The threshold select logic sets the threshold to a first value when the first portion is being written and sets the threshold to a second value, greater than the first value, when the second portion is being written. Because different thresholds are assoicated with the portions, data, such as a digitized video signal having active line portions separated by control portions for example, can be transferred via the FIFO from one system to another more efficiently in terms of communication bandwidth usage.

REFERENCES:
patent: 4507760 (1985-03-01), Fraser
patent: 4694426 (1987-09-01), Mason
patent: 4833651 (1989-05-01), Seltzer et al.
patent: 4862419 (1989-08-01), Hoberman
patent: 4864543 (1989-09-01), Ward et al.
patent: 4888739 (1989-12-01), Frederick et al.
patent: 4888741 (1989-12-01), Malinowski
patent: 4891788 (1990-01-01), Kreifels
patent: 4942553 (1990-07-01), Dalrymple et al.
patent: 4969164 (1990-11-01), Mehta et al.
patent: 5121480 (1992-06-01), Bonke et al.
Barbour et a., "A Parallel, High Speed Circular Queue Structure", Proceedings of 32nd Midwest Symposium on Circuits and Systems, vol. 21, Aug. 1989, pp. 1089-1092.

Affiliated with

Also associated with

Rating

FIFO memory controller for a digital video communications channe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FIFO memory controller for a digital video communications channe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO memory controller for a digital video communications channe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2217899