FIFO memory capable of simultaneously selecting a plurality of w

Details FIFO memory capable of simultaneously selecting a plurality of w FIFO memory capable of simultaneously selecting a plurality of w

1988-09-16

1990-09-04

Gossage, Glenn A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

3652385, 365240, 365221, 365201, G11C 800

Patent

active

049549944

ABSTRACT:
A semiconductor memory device is constructed so that a plurality of word lines may be simultaneously selected by the transfer of information through a plurality of shift register positions of a shift register, wherein the respective shift register positions are connected to individual word lines. Simultaneously with the selection of the word lines, data may be written in or readout from the memory. The shift register is part of an address decoder which also includes logic circuits providing first and second selector devices. The first selector device is connected between a control circuit and the initial shift register position, while the second selector device is connected between the control circuit and each of the plurality of shift register positions arranged in parallel. When the first selector device is activated by a first control signal from the control circuit, binary data is clocked through each of the shift register positions. Then, a second control signal activates the second selector device for producing an output signal to each of the shift register positions, thereby applying the information thereof to the word lines and simultaneously selecting those word lines corresponding to shift register positions in which a logic "1" has been stored.

REFERENCES:
patent: 4562435 (1985-12-01), McDonough et al.
patent: 4670878 (1987-06-01), Childers
patent: 4744058 (1988-05-01), Kawashima et al.
patent: 4799198 (1989-01-01), Ogawa
Pai, "FIFO RAM Controller Tackles Deep Data Buffering", Computer Design, Aug. 1, 1986, pp. 109-112.
Tunick, "Rich with Logic, Memory ICs Hone Their Specialties", Electronic Design, Jun. 11, 1987, pp. 77-86.
"A 1Mb Dram with 33MHz Serial I/O Ports"-Ohta et al., IEEE International Solid-State Circuits Conference, pp. 274-275 (Feb. 21, 1986) with related product description 1 Mbit Image Memory MN4700 Product Description.
"1985 Memory Products Databook"-NEC Electronics Inc., .mu. PD41221 224, 000-Bit Serial-Access NMOS RAM, pp. 3-21 through 3-25 (Jan. 1985).
"1986 Memory Databook"-NEC Electronics Inc., .mu. PD41221 224,000-Bit Serial-Access NMOS RAM, pp. 3-25 through 3-31 (Apr. 1986).

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